[Intel-gfx] [PATCH 00/31] shared pch display pll rework

[Daniel Vetter]

Hi all,

So originally I've only set out to create a more paranoid version of Jesse's hw
state reconstruction for the shared pch display plls. But then I've noticed that
the current code still smells broken (very first patch) and decided that we
should abstract the refcounting and hw state readout/compare logic from the
platform details a bit, so that we can reuse it on e.g. Haswell.

Since it's tricky code, it's split up in a lot of rather small patches itching
forward towards the goal. In the end we have
- new vfuncs to hide the platform details for ->enable/disable/mode_set of a
  shared display pll.
- hw state readout and compare for both the display plls alone and their
  use by display pipes.

Not yet done is:
- Moving the pll selection logic into the compute config stage of the modeset
  sequence. So atomic modeset still needs more work, we only notice the lack of
  a suitable dpll in the mode_set stage.
- Seperating the platform logic to pick a suitable from the get refcounting.
  This might be needed for Haswell (but I'm not sure yet how to best map the
  different Haswell plls).
- Convert Haswell ddi pll code over to this so that fastboot/atomic modeset can
  work there, too.

Series contains a few parts:

- patch 1: Fixup modeset on a shared dpll - we could change the dpll config if
  it's in use by another pipe.
- patches 2-7: Prep work, improved assert checks and moving the current state
  into the pipe_config (but not yet taking advantage of that at all).
- patches 8-13: Refactor the shared dpll code and add ->enable/disable hooks.
- patches 14-17: Basic (i.e. on/off) state readout for shared dplls + a bit of
  follow-up cleanup.
- patches 18-22: hw state readout for the full register state and follow-up
  cleanups taking advantage of that. By this point fastboot has enough state
  recovered to correctly take over pch dplls from the bios. While doing so I've
  also aligned the ilk+ pch pll enable sequenc with the i9xx dpll enable
  sequence - too much cargo cult seems to have added a bit of cruft on the ilk
  paths.
- patches 23-29: Since I've banged my head badly against the lvds enabling
  sequence while developing the above I've figured I'll clean up that mess (and
  bake the hard-learned lessons into code with asserts). It also fixes the pll
  enabling sequence on vlv/i9xx, so at the end we no longer call an ->enable
  function anywhere from ->mode_set!
- patches 30-31: Two afterthoughts on top ;-)

Comments, flames, testing and review highly welcome.

Cheers, Daniel

Daniel Vetter (31):
  drm/i915: fix up pch pll handling in ->mode_set
  drm/i915: conditionally disable pch resources in ilk_crtc_disable
  drm/i915: lock down pch pll accouting some more
  drm/i915: s/pch_pll/shared_dpll/
  drm/i915: switch crtc->shared_dpll from a pointer to an enum
  drm/i915: move shared_dpll into the pipe config
  drm/i915: refactor PCH_DPLL_SEL #defines
  drm/i915: hw state readout for shared pch plls
  drm/i915: consolidate ->num_shared_dplls assignement
  drm/i915: metadata for shared dplls
  drm/i915: scrap register address storage
  drm/i915: enable/disable hooks for shared dplls
  drm/i915: drop crtc checking from assert_shared_dpll
  drm/i915: display pll hw state readout and checking
  drm/i915: extract readout_hw_state from setup_hw_state
  drm/i915: split up intel_modeset_check_state
  drm/i915: WARN on lack of shared dpll
  drm/i915: hw state readout and cross-checking for shared dplls
  drm/i915: fix up pch pll enabling for pixel multipliers
  drm/i915: simplify the reduced clock handling for pch plls
  drm/i915: consolidate pch pll enable sequence
  drm/i915: use sw tracked state to select shared dplls
  drm/i915: duplicate intel_enable_pll into i9xx and vlv versions
  drm/i915: asserts for lvds pre_enable
  drm/i915: move encoder pre enable hooks togther on ilk+
  drm/i915: hw state readout for i9xx dplls
  drm/i915: move i9xx dpll enabling into crtc enable function
  drm/i915: s/pre_pll/pre/ on the lvds port enable function
  drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence
  drm/i915: Fix up cpt pixel multiplier enable sequence
  drm/i915: clear DPLL reg when disabling i9xx dplls

 drivers/gpu/drm/i915/i915_drv.c      |   7 -
 drivers/gpu/drm/i915/i915_drv.h      |  42 +-
 drivers/gpu/drm/i915/i915_reg.h      |  18 +-
 drivers/gpu/drm/i915/i915_ums.c      |   2 +-
 drivers/gpu/drm/i915/intel_display.c | 853 ++++++++++++++++++++---------------
 drivers/gpu/drm/i915/intel_drv.h     |  24 +-
 drivers/gpu/drm/i915/intel_lvds.c    |  21 +-
 7 files changed, 573 insertions(+), 394 deletions(-)

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1.7.11.7