[Intel-gfx] [PATCH 20/31] drm/i915: simplify the reduced clock handling for pch plls

[Daniel Vetter]

Just move the lowfreq_avail logic out of the register writing as a
prep step for the next patch, which will coalesce all the pch pll
enabling into one spot.

Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ecf0b1e..fc1b5f7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5686,7 +5686,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		if (encoder->pre_pll_enable)
 			encoder->pre_pll_enable(encoder);
 
-	intel_crtc->lowfreq_avail = false;
+	if (is_lvds && has_reduced_clock && i915_powersave)
+		intel_crtc->lowfreq_avail = true;
+	else
+		intel_crtc->lowfreq_avail = false;
 
 	if (intel_crtc->config.has_pch_encoder) {
 		pll = intel_crtc_to_shared_dpll(intel_crtc);
@@ -5704,12 +5707,10 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
 		 */
 		I915_WRITE(PCH_DPLL(pll->id), dpll);
 
-		if (is_lvds && has_reduced_clock && i915_powersave) {
+		if (has_reduced_clock)
 			I915_WRITE(PCH_FP1(pll->id), fp2);
-			intel_crtc->lowfreq_avail = true;
-		} else {
+		else
 			I915_WRITE(PCH_FP1(pll->id), fp);
-		}
 	}
 
 	intel_set_pipe_timings(intel_crtc);
-- 
1.7.11.7