[Intel-gfx] [PATCH 23/31] drm/i915: duplicate intel_enable_pll into i9xx and vlv versions

[Jani Nikula]

On Wed, 05 Jun 2013, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> Mostly since I _really_ don't want to touch the vlv hell.
>
> No code change, just duplication. Also kill a now seriously outdated
> code comment - the remark about the dvo encoder is now handled with
> the pipe A quirk.
>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 49 ++++++++++++++++++++++++------------
>  1 file changed, 33 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4d2284e..5d84fea 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1271,20 +1271,37 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
>  	assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
>  }
>  
> -/**
> - * intel_enable_pll - enable a PLL
> - * @dev_priv: i915 private structure
> - * @pipe: pipe PLL to enable
> - *
> - * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
> - * make sure the PLL reg is writable first though, since the panel write
> - * protect mechanism may be enabled.
> - *
> - * Note!  This is for pre-ILK only.
> - *
> - * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
> - */
> -static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> +static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> +{
> +	int reg;
> +	u32 val;
> +
> +	assert_pipe_disabled(dev_priv, pipe);
> +
> +	/* No really, not for ILK+ */
> +	BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);

Could be made BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));

Jani.

> +
> +	/* PLL is protected by panel, make sure we can write it */
> +	if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
> +		assert_panel_unlocked(dev_priv, pipe);
> +
> +	reg = DPLL(pipe);
> +	val = I915_READ(reg);
> +	val |= DPLL_VCO_ENABLE;
> +
> +	/* We do this three times for luck */
> +	I915_WRITE(reg, val);
> +	POSTING_READ(reg);
> +	udelay(150); /* wait for warmup */
> +	I915_WRITE(reg, val);
> +	POSTING_READ(reg);
> +	udelay(150); /* wait for warmup */
> +	I915_WRITE(reg, val);
> +	POSTING_READ(reg);
> +	udelay(150); /* wait for warmup */
> +}
> +
> +static void i9xx_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
>  {
>  	int reg;
>  	u32 val;
> @@ -3535,7 +3552,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
>  		if (encoder->pre_pll_enable)
>  			encoder->pre_pll_enable(encoder);
>  
> -	intel_enable_pll(dev_priv, pipe);
> +	vlv_enable_pll(dev_priv, pipe);
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->pre_enable)
> @@ -3578,7 +3595,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
>  	intel_crtc->active = true;
>  	intel_update_watermarks(dev);
>  
> -	intel_enable_pll(dev_priv, pipe);
> +	i9xx_enable_pll(dev_priv, pipe);
>  
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->pre_enable)
> -- 
> 1.7.11.7
>
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