[Intel-gfx] [PATCH 2/2] drm/i915: hw state readout support for pixel_multiplier

[Daniel Vetter]

On Wed, Jun 05, 2013 at 06:01:57PM +0300, Imre Deak wrote:
> On Sat, 2013-06-01 at 17:17 +0200, Daniel Vetter wrote:
> > Incomplete since ilk+ support needs proper pch dpll tracking first.
> > SDVO get_config parts based on a patch from Jesse Barnes, but fixed up
> > to actually work.
> > 
> > Cc: Jesse Barnes <jbarnes at virtuousgeek.org>
> > Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 25 +++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_sdvo.c    | 30 +++++++++++++++++++++++++++++-
> >  2 files changed, 54 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 9f772eb..f126e18 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -4965,6 +4965,23 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> >  
> >  	i9xx_get_pfit_config(crtc, pipe_config);
> >  
> > +	if (INTEL_INFO(dev)->gen >= 4) {
> > +		tmp = I915_READ(DPLL_MD(crtc->pipe));
> > +		pipe_config->pixel_multiplier =
> > +			((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
> > +			 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
> > +	} else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
> > +		tmp = I915_READ(DPLL(crtc->pipe));
> > +		pipe_config->pixel_multiplier =
> > +			((tmp & SDVO_MULTIPLIER_MASK)
> > +			 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
> > +	} else {
> > +		/* Note that on i915G/GM the pixel multiplier is in the sdvo
> > +		 * port and will be fixed up in the encoder->get_config
> > +		 * function. */
> > +		pipe_config->pixel_multiplier = 1;
> > +	}
> > +
> >  	return true;
> >  }
> >  
> > @@ -5828,6 +5845,12 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
> >  					  FDI_DP_PORT_WIDTH_SHIFT) + 1;
> >  
> >  		ironlake_get_fdi_m_n_config(crtc, pipe_config);
> > +
> > +		/* XXX: Can't properly read out the pch dpll pixel multiplier
> > +		 * since we don't have state tracking for pch clocks yet. */
> > +		pipe_config->pixel_multiplier = 1;
> > +	} else {
> > +		pipe_config->pixel_multiplier = 1;
> >  	}
> >  
> >  	intel_get_pipe_timings(crtc, pipe_config);
> > @@ -5980,6 +6003,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
> >  	pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
> >  				   (I915_READ(IPS_CTL) & IPS_ENABLE);
> >  
> > +	pipe_config->pixel_multiplier = 1;
> > +
> >  	return true;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> > index f4588a2..5c816dd 100644
> > --- a/drivers/gpu/drm/i915/intel_sdvo.c
> > +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> > @@ -1313,9 +1313,13 @@ static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
> >  static void intel_sdvo_get_config(struct intel_encoder *encoder,
> >  				  struct intel_crtc_config *pipe_config)
> >  {
> > +	struct drm_device *dev = encoder->base.dev;
> > +	struct drm_i915_private *dev_priv = dev->dev_private;
> >  	struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
> >  	struct intel_sdvo_dtd dtd;
> > -	u32 flags = 0;
> > +	int encoder_pixel_multiplier = 0;
> > +	u32 flags = 0, sdvox;
> > +	u8 val;
> >  	bool ret;
> >  
> >  	ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
> > @@ -1335,6 +1339,30 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
> >  		flags |= DRM_MODE_FLAG_NVSYNC;
> >  
> >  	pipe_config->adjusted_mode.flags |= flags;
> > +
> > +	if (IS_I915G(dev) || IS_I915GM(dev)) {
> > +		sdvox = I915_READ(intel_sdvo->sdvo_reg);
> > +		pipe_config->pixel_multiplier =
> > +			((sdvox & SDVO_PORT_MULTIPLY_MASK)
> > +			 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
> > +	}
> > +
> > +	/* Cross check the port pixel multiplier with the sdvo encoder state. */
> > +	intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1);
> > +	switch (val) {
> > +	case SDVO_CLOCK_RATE_MULT_1X:
> > +		encoder_pixel_multiplier = 1;
> > +		break;
> > +	case SDVO_CLOCK_RATE_MULT_2X:
> > +		encoder_pixel_multiplier = 2;
> > +		break;
> > +	case SDVO_CLOCK_RATE_MULT_4X:
> > +		encoder_pixel_multiplier = 4;
> > +		break;
> > +	}
> > +	WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
> > +	     "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
> > +	     pipe_config->pixel_multiplier, encoder_pixel_multiplier);
> >  }
> 
> In intel_modeset_check_state() we call first encoder->get_config() and
> only afterwards display->get_pipe_config(), so this won't work on
> I915G/GM.

Meh, I've forgotten about this. In setup_hw_state the order is the correct
one, but the check_state stuff is wrong. I'll do what I've asked Jesse to
do and move that encoder->get_config call into the crtc_get_config
functions so that we always have the same (hopefully right ordering).

> Other than that the 2 patches look ok:
> Reviewed-by: Imre Deak <imre.deak at intel.com>

Thanks for the review. I'll merge the first patch right away, imo it's a
nice stand-alone cleanup.

> Related but not affecting my r-b:
> The multiplier can take all values from 1-5, why aren't we handling all?
> Should we add the proper check to intel_pipe_config_compare() too?

intel_sdvo_get_pixel_multiplier in intel_sdvo.c only sets these 3 cases,
and iirc the sdvo spec mentions that those are the only ones. HDMI otoh
can take odd multipliers, too. I guess that's why the dpll_md (and other
fields) can take those values. But currently we don't support modes with
multiplied pixels.

Yours, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch