[Intel-gfx] [PATCH 10/10] drm/i915: Implement WaBlockMsgChannelDuringGfxReset

[Damien Lespiau]

Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 9 +++++++++
 drivers/gpu/drm/i915/i915_reg.h | 9 +++++++--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 58048d4..187a9a4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4063,6 +4063,15 @@ i915_gem_init_hw(struct drm_device *dev)
 		I915_WRITE(GEN7_MSG_CTL, temp);
 	}
 
+	/* WaBlockMsgChannelDuringGfxReset:hsw */
+	if (IS_HASWELL(dev)) {
+		u32 temp = I915_READ(GEN7_MISCCPCTL);
+		temp &= MISCCPCTL_BLOCK_MC_GFX_FULL_SR |
+			MISCCPCTL_BLOCK_MC_RENDER_SR |
+			MISCCPCTL_BLOCK_MC_FLR;
+		I915_WRITE(GEN7_MISCCPCTL, temp);
+	}
+
 	i915_gem_l3_remap(dev);
 
 	i915_gem_init_swizzling(dev);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47a9de0..ff27c73 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4595,8 +4595,13 @@
 #define   GEN6_RC6			3
 #define   GEN6_RC7			4
 
-#define GEN7_MISCCPCTL			(0x9424)
-#define   GEN7_DOP_CLOCK_GATE_ENABLE	(1<<0)
+#define GEN7_MISCCPCTL				(0x9424)
+#define   MISCCPCTL_BLOCK_MC_GFX_FULL_SR	(1<<6)
+#define   MISCCPCTL_BLOCK_MC_BLITTER_SR		(1<<5)
+#define   MISCCPCTL_BLOCK_MC_MEDIA_SR		(1<<4)
+#define   MISCCPCTL_BLOCK_MC_RENDER_SR		(1<<3)
+#define   MISCCPCTL_BLOCK_MC_FLR		(1<<2)
+#define   GEN7_DOP_CLOCK_GATE_ENABLE		(1<<0)
 
 /* IVYBRIDGE DPF */
 #define GEN7_L3CDERRST1			0xB008 /* L3CD Error Status 1 */
-- 
1.8.1.4