[Intel-gfx] [PATCH 3/3] drm/i915: Fix checking of pixel multiplier on SDVOX

Daniel Vetter daniel at ffwll.ch
Sun Jun 9 21:48:11 CEST 2013


On Sun, Jun 9, 2013 at 7:23 PM, Chris Wilson <chris at chris-wilson.co.uk> wrote:
> The pixel multiplier is only stored in SDVOX on i915g/i915gm, so we need
> to use the value retreived from the card for pipe_config and restrict
> the cross check to i915g/i915gm.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>

Failing this cross check was a fallout from the incosistent ordering
of the get_pipe_config vs. encoder->get_config calls in setup_hw_state
vs. modeset_check_state. It should be fixed in latest dinq, at least
it seemed to on my g33 and i915g.

Note that you can't yet cross-check the pixel multiplier on PCH_SPLIT
platforms since we lack the hw state readout code there ... But I
don't have hw to test that, so if you could give my stuff branch a
whirl, that should be interesting.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_sdvo.c |   34 ++++++++++++++++++----------------
>  1 file changed, 18 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index d03c471..abd6697 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -1320,8 +1320,7 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
>         struct drm_i915_private *dev_priv = dev->dev_private;
>         struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
>         struct intel_sdvo_dtd dtd;
> -       int encoder_pixel_multiplier = 0;
> -       u32 flags = 0, sdvox;
> +       u32 flags = 0;
>         u8 val;
>         bool ret;
>
> @@ -1345,29 +1344,32 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
>
>         pipe_config->adjusted_mode.flags |= flags;
>
> -       if (IS_I915G(dev) || IS_I915GM(dev)) {
> -               sdvox = I915_READ(intel_sdvo->sdvo_reg);
> -               pipe_config->pixel_multiplier =
> -                       ((sdvox & SDVO_PORT_MULTIPLY_MASK)
> -                        >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
> -       }
> -
> -       /* Cross check the port pixel multiplier with the sdvo encoder state. */
>         intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, &val, 1);
>         switch (val) {
>         case SDVO_CLOCK_RATE_MULT_1X:
> -               encoder_pixel_multiplier = 1;
> +               pipe_config->pixel_multiplier = 1;
>                 break;
>         case SDVO_CLOCK_RATE_MULT_2X:
> -               encoder_pixel_multiplier = 2;
> +               pipe_config->pixel_multiplier = 2;
>                 break;
>         case SDVO_CLOCK_RATE_MULT_4X:
> -               encoder_pixel_multiplier = 4;
> +               pipe_config->pixel_multiplier = 4;
>                 break;
>         }
> -       WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
> -            "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
> -            pipe_config->pixel_multiplier, encoder_pixel_multiplier);
> +
> +       /* Cross check the port pixel multiplier with the sdvo encoder state. */
> +       if (IS_I915G(dev) || IS_I915GM(dev)) {
> +               u32 port_pixel_multiplier;
> +
> +               port_pixel_multiplier = I915_READ(intel_sdvo->sdvo_reg);
> +               port_pixel_multiplier &= SDVO_PORT_MULTIPLY_MASK;
> +               port_pixel_multiplier >>= SDVO_PORT_MULTIPLY_SHIFT;
> +               port_pixel_multiplier += 1;
> +
> +               WARN(port_pixel_multiplier != pipe_config->pixel_multiplier,
> +                    "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
> +                    port_pixel_multiplier, pipe_config->pixel_multiplier);
> +       }
>  }
>
>  static void intel_disable_sdvo(struct intel_encoder *encoder)
> --
> 1.7.10.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx



--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch



More information about the Intel-gfx mailing list