[Intel-gfx] [PATCH 5/9] drm/i915: pnv dpll doesn't use m1!

[Damien Lespiau]

On Tue, May 21, 2013 at 09:54:55PM +0200, Daniel Vetter wrote:
> So don't try to store it in the DPLL_FP register.
> 
> Otherwise it looks like the limits for pineview are correct: It has
> it's own clock computation code, which doesn't use an offset for n
> divisors, and the register value based m limits look sane enough.

  - n can vary between 2 and 6, but we declare the 3-6 as limits.
  - p1 seems to be able to go up to 9
  - the m upper limit seems a bit big, but the docs are a bit shy on
    that values for pnv.

Otherwise, the change itself seems good:

Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>

> 
> v2: Rebase on top of the pineview clock refactor and fixup up the
> commit message: It's m1 pnv doens't care about, not m2!
> 
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index cb54131..520e340 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4300,7 +4300,7 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
>  
>  static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
>  {
> -	return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
> +	return (1 << dpll->n) << 16 | dpll->m2;
>  }
>  
>  static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
> -- 
> 1.7.11.7
> 
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