[Intel-gfx] [PATCH] drm/i915: Fix VLV analog output shivers

[Daniel Vetter]

On Wed, Jun 12, 2013 at 10:14 AM, Ville Syrjälä
<ville.syrjala at linux.intel.com> wrote:
> On Tue, Jun 11, 2013 at 04:18:46PM -0700, Jesse Barnes wrote:
>> On Tue, 11 Jun 2013 23:06:59 +0200
>> Daniel Vetter <daniel at ffwll.ch> wrote:
>>
>> > On Tue, Jun 11, 2013 at 11:08:16PM +0300, ville.syrjala at linux.intel.com wrote:
>> > > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>> > >
>> > > The current PLL settings produce a rather unstable picture when
>> > > I hook up a VLV to my HP ZR24w display via a VGA cable. Switching
>> > > the PLL to hybrid mode makes the picture a lot more stable. No
>> > > idea if this is truly wise though...
>> >
>> > Ok, you've just slipped up here and mentioned that the changed bit is for
>> > "hybrid mode". Can I have real register defines for this magic now please?
>> >
>> > Apparently Jesse just weaseled out of real work claiming that it's not
>> > documented at all ;-)
>> >
>>
>> There are some bits we could use, but we'd be making up the name.  On
>> top of that, the hex value is used in the docs, so if we make up bit
>> field names, we'll end up double taking everytime we look at these bits.
>>
>> So there's no good answer here... :/
>
> For this particular register I've not seen any documented "correct"
> value. I have no idea where the values used in the code came from. If
> you have a document that has them, I'd like to see it.
>
> There are certainly some register values that are specified as raw hex
> numbers in some docs, but I've noticed that in some cases even those
> don't agree with our code :(

Yeah, I'd prefer if we can slowly move to less magic. It's more work
to fill updates from the validation guys into patches, otoh it should
help greatly to reduce accidental breakage. And if regressions start
to hit us we might have a stab at a sensible revert.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch