[Intel-gfx] [PATCH] drm/i915: "Scotty, I need more power!"

[Jesse Barnes]

"I'm giving her all she's got!"

This patch adds a new module param, enable_turbo, which allows the user
to disable the hw assisted frequency selection system and just run at
the max frequency whenever the GPU is active.  It won't affect RC6, so
when the GPU goes idle, it should still shut down and save power.

But keep in mind Scotty's warning too:

"She cannae take more Captain, she's gonna blow!"

I.e. this may cause the package to hit thermal and/or power limits,
leading to throttling by the Punit, which could lead to latency spikes
or unpredictable performance.

Requested-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
 drivers/gpu/drm/i915/i915_drv.c |    4 +++
 drivers/gpu/drm/i915/i915_drv.h |    1 +
 drivers/gpu/drm/i915/intel_pm.c |   54 +++++++++++++++++++++++----------------
 3 files changed, 37 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 062cbda..e538a8a 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -132,6 +132,10 @@ int i915_enable_ips __read_mostly = 1;
 module_param_named(enable_ips, i915_enable_ips, int, 0600);
 MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
 
+bool i915_enable_turbo __read_mostly = 1;
+module_param_named(enable_turbo, i915_enable_turbo, bool, 0600);
+MODULE_PARM_DESC(enable_turbo, "Enable GPU turbo (default: true)");
+
 static struct drm_driver driver;
 extern int intel_agp_enabled;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e9c8b58..5655fcb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1546,6 +1546,7 @@ extern int i915_enable_ppgtt __read_mostly;
 extern unsigned int i915_preliminary_hw_support __read_mostly;
 extern int i915_disable_power_well __read_mostly;
 extern int i915_enable_ips __read_mostly;
+extern bool i915_enable_turbo __read_mostly;
 
 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
 extern int i915_resume(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aa48fc6..e809c57 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3323,19 +3323,25 @@ static void gen6_enable_rps(struct drm_device *dev)
 		DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
 	}
 
-	gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
-
-	/* requires MSI enabled */
-	I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS);
-	spin_lock_irq(&dev_priv->rps.lock);
-	/* FIXME: Our interrupt enabling sequence is bonghits.
-	 * dev_priv->rps.pm_iir really should be 0 here. */
-	dev_priv->rps.pm_iir = 0;
-	I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
-	I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
-	spin_unlock_irq(&dev_priv->rps.lock);
-	/* unmask all PM interrupts */
-	I915_WRITE(GEN6_PMINTRMSK, 0);
+	if (i915_enable_turbo) {
+		gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
+
+		/* requires MSI enabled */
+		I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) |
+			   GEN6_PM_RPS_EVENTS);
+		spin_lock_irq(&dev_priv->rps.lock);
+		/* FIXME: Our interrupt enabling sequence is bonghits.
+		 * dev_priv->rps.pm_iir really should be 0 here. */
+		dev_priv->rps.pm_iir = 0;
+		I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) &
+			   ~GEN6_PM_RPS_EVENTS);
+		I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
+		spin_unlock_irq(&dev_priv->rps.lock);
+		/* unmask all PM interrupts */
+		I915_WRITE(GEN6_PMINTRMSK, 0);
+	} else {
+		gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
+	}
 
 	rc6vids = 0;
 	ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
@@ -3603,16 +3609,20 @@ static void valleyview_enable_rps(struct drm_device *dev)
 
 	INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
 
-	valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
+	if (i915_enable_turbo) {
+		valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
 
-	/* requires MSI enabled */
-	I915_WRITE(GEN6_PMIER, GEN6_PM_RPS_EVENTS);
-	spin_lock_irq(&dev_priv->rps.lock);
-	WARN_ON(dev_priv->rps.pm_iir != 0);
-	I915_WRITE(GEN6_PMIMR, 0);
-	spin_unlock_irq(&dev_priv->rps.lock);
-	/* enable all PM interrupts */
-	I915_WRITE(GEN6_PMINTRMSK, 0);
+		/* requires MSI enabled */
+		I915_WRITE(GEN6_PMIER, GEN6_PM_RPS_EVENTS);
+		spin_lock_irq(&dev_priv->rps.lock);
+		WARN_ON(dev_priv->rps.pm_iir != 0);
+		I915_WRITE(GEN6_PMIMR, 0);
+		spin_unlock_irq(&dev_priv->rps.lock);
+		/* enable all PM interrupts */
+		I915_WRITE(GEN6_PMINTRMSK, 0);
+	} else {
+		valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
+	}
 
 	gen6_gt_force_wake_put(dev_priv);
 }
-- 
1.7.9.5