[Intel-gfx] [PATCH 25/28] drm/i915/dp: program VSwing and Preemphasis control settings on VLV

[Jesse Barnes]

From: Pallavi G <pallavi.g at intel.com>

Program few Tx buffer Swing control settings through DPIO.

Signed-off-by: Pallavi G <pallavi.g at intel.com>
Signed-off-by: Yogesh M <yogesh.mohan.marimuthu at intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat at intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c |  114 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 112 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 68d238d..03340fd 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1527,7 +1527,9 @@ intel_dp_voltage_max(struct intel_dp *intel_dp)
 {
 	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 
-	if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
+	if (IS_VALLEYVIEW(dev))
+		return DP_TRAIN_VOLTAGE_SWING_1200;
+	else if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
 		return DP_TRAIN_VOLTAGE_SWING_800;
 	else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
 		return DP_TRAIN_VOLTAGE_SWING_1200;
@@ -1552,7 +1554,19 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 		default:
 			return DP_TRAIN_PRE_EMPHASIS_0;
 		}
-	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
+	} else if (IS_VALLEYVIEW(dev)) {
+		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			return DP_TRAIN_PRE_EMPHASIS_9_5;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			return DP_TRAIN_PRE_EMPHASIS_6;
+		case DP_TRAIN_VOLTAGE_SWING_800:
+			return DP_TRAIN_PRE_EMPHASIS_3_5;
+		case DP_TRAIN_VOLTAGE_SWING_1200:
+		default:
+			return DP_TRAIN_PRE_EMPHASIS_0;
+		}
+	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) {
 		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 		case DP_TRAIN_VOLTAGE_SWING_400:
 			return DP_TRAIN_PRE_EMPHASIS_6;
@@ -1577,15 +1591,111 @@ intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
 	}
 }
 
+static void vlv_set_vswing_pre_emphasis(struct intel_dp *intel_dp, uint8_t v,
+					uint8_t p)
+{
+	struct drm_device *dev = intel_dp_to_dev(intel_dp);
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	unsigned long Demph_reg_value, Preemph_reg_value,
+		Uniqtranscale_reg_value;
+	switch (p) {
+	case DP_TRAIN_PRE_EMPHASIS_0:
+		Preemph_reg_value = 0x0004000;
+		switch (v) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			Demph_reg_value = 0x2B405555;
+			Uniqtranscale_reg_value = 0x552AB83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			Demph_reg_value = 0x2B404040;
+			Uniqtranscale_reg_value = 0x5548B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_800:
+			Demph_reg_value = 0x2B245555;
+			Uniqtranscale_reg_value = 0x5560B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_1200:
+			Demph_reg_value = 0x2B405555;
+			Uniqtranscale_reg_value = 0x5598DA3A;
+			break;
+		default:
+			return;
+		}
+		break;
+	case DP_TRAIN_PRE_EMPHASIS_3_5:
+		Preemph_reg_value = 0x0002000;
+		switch (v) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			Demph_reg_value = 0x2B404040;
+			Uniqtranscale_reg_value = 0x5552B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			Demph_reg_value = 0x2B404848;
+			Uniqtranscale_reg_value = 0x5580B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_800:
+			Demph_reg_value = 0x2B404040;
+			Uniqtranscale_reg_value = 0x55ADDA3A;
+			break;
+		default:
+			return;
+		}
+		break;
+	case DP_TRAIN_PRE_EMPHASIS_6:
+		Preemph_reg_value = 0x0000000;
+		switch (v) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			Demph_reg_value = 0x2B305555;
+			Uniqtranscale_reg_value = 0x5570B83A;
+			break;
+		case DP_TRAIN_VOLTAGE_SWING_600:
+			Demph_reg_value = 0x2B2B4040;
+			Uniqtranscale_reg_value = 0x55ADDA3A;
+			break;
+		default:
+			return;
+		}
+		break;
+	case DP_TRAIN_PRE_EMPHASIS_9_5:
+		Preemph_reg_value = 0x0006000;
+		switch (v) {
+		case DP_TRAIN_VOLTAGE_SWING_400:
+			Demph_reg_value = 0x1B405555;
+			Uniqtranscale_reg_value = 0x55ADDA3A;
+			break;
+		default:
+			return;
+		}
+		break;
+	default:
+		return;
+	}
+
+	/* eDP is only on port C */
+	mutex_lock(&dev_priv->dpio_lock);
+	intel_dpio_write(dev_priv, 0x8494, 0x00000000);
+	intel_dpio_write(dev_priv, 0x8490, Demph_reg_value);
+	intel_dpio_write(dev_priv, 0x8488, Uniqtranscale_reg_value);
+	intel_dpio_write(dev_priv, 0x848c, 0x0C782040);
+	intel_dpio_write(dev_priv, 0x842c, 0x00030000);
+	intel_dpio_write(dev_priv, 0x8424, Preemph_reg_value);
+	intel_dpio_write(dev_priv, 0x8494, 0x80000000);
+	mutex_unlock(&dev_priv->dpio_lock);
+}
+
 static void
 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
 {
+	struct drm_device *dev = intel_dp_to_dev(intel_dp);
 	uint8_t v = 0;
 	uint8_t p = 0;
 	int lane;
 	uint8_t voltage_max;
 	uint8_t preemph_max;
 
+	if (IS_VALLEYVIEW(dev))
+		vlv_set_vswing_pre_emphasis(intel_dp, v, p);
+
 	for (lane = 0; lane < intel_dp->lane_count; lane++) {
 		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
 		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
-- 
1.7.9.5