[Intel-gfx] [PATCH 04/26] drm/i915: update VLV PLL and DPIO code

[Jesse Barnes]

On Fri,  1 Mar 2013 14:08:20 -0800
Jesse Barnes <jbarnes at virtuousgeek.org> wrote:

> From: Pallavi G <pallavi.g at intel.com>
> 
> In Valleyview voltage swing, pre-emphasis and lane control registers can
> be programmed only through the h/w side band fabric.  Update
> vlv_update_pll, i9xx_crtc_enable, and intel_enable_pll with the
> appropriate programming.
> 
> We need to make sure that the tx lane reset occurs in both the full mode
> set and DPMS paths, so factor things out to allow that.
> 
> v2: use different DPIO_DIVISOR values for VGA and DisplayPort
> v3: Fix update pll logic to use same DPIO_DIVISOR & DPIO_REFSFR values
> 	for all display interfaces
> v4: collapse with various updates
> v5: squash with crtc enable/pll enable bits

Reviewing myself:
  - port phyready needs to be conditional on vlv (probably extracted
    into a separate fn)
  - early port enable should be vlv only (may not be necessary, need to
    test)

-- 
Jesse Barnes, Intel Open Source Technology Center