[Intel-gfx] [PATCH 07/26] drm/i915: implement WaDisablePSDDualDispatchEnable on VLV

[Ville Syrjälä]

On Fri, Mar 01, 2013 at 02:08:23PM -0800, Jesse Barnes wrote:
> Can prevent a hang when we get to tessellation.
> 
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> ---
>  drivers/gpu/drm/i915/intel_pm.c |    4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 61fee7f..59ea12a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3899,8 +3899,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
>  		   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
>  		   CHICKEN3_DGMG_DONE_FIX_DISABLE);
>  
> +	/* WaDisablePSDDualDispatchEnable */
>  	I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
> -		   _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
> +		   _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
> +				      GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));

The comment added matches what we already did. But the thread dep stuff
seems to be something else. It seems to match the default value anyway,
so shouldn't be needed AFAICS.

>  
>  	/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
>  	I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
> -- 
> 1.7.9.5
> 
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-- 
Ville Syrjälä
Intel OTC