[Intel-gfx] commit drm/i915: disable shared panel fitter for pipe breaks resolution switching
Hans de Bruin
jmdebruin at xmsnet.nl
Thu Mar 7 20:12:26 CET 2013
On 03/06/2013 11:37 PM, Daniel Vetter wrote:
> On Wed, Mar 6, 2013 at 7:39 PM, Hans de Bruin <jmdebruin at xmsnet.nl> wrote:
>> On 03/06/2013 03:00 PM, Daniel Vetter wrote:
>>>
>>> Hi Hans,
>>>
>>> Can you please test with 3.9-rc1? That contains an additional patch
>>> which might prevent the regression. Specifically
>>>
>>> commit 9d6d9f19e8146fa24903cb561e204a22232740e3
>>> Author: Mika Kuoppala <mika.kuoppala at linux.intel.com>
>>> Date: Fri Feb 8 16:35:38 2013 +0200
>>>
>>> drm/i915: clean up panel fitter handling in lvds
>>
>>
>> Today's kernel still contains the bug.
>
> Hm, I've just retested latest drm-intel-nightly which should have the
> same set of relevant patches, and I couldn't reproduce your issue.
> Low-res modes on the lvds panel seem to correctly scale up here on my
> 945gm.
dell latitudes d430's are quite special.
>
> Can you pls retest with latest -nightly from
> http://cgit.freedesktop.org/~danvet/drm-intel ?
>
pending
> Also please attach the output of xrandr --verbose when running with a
> reduced mode.
I have attached the output of xrandr and intel_reg_dumper good and bad.
People have asked for intel_reg_dumper output before. I do not know
whether color things show up in the dump but I also have a color
problem. That problem is not caused by this commit.
--
Hans
-------------- next part --------------
PGETBL_CTL: 0x7ffc0001
PGTBL_ER: 0x00000000
EXCC: 0x00000000
HWS_PGA: 0x36200000
IPEIR: 0x00000000
IPEHR: 0x01000000
INST_DONE: 0x7fffffc0
NOPID: 0x00000000
HWSTAM: 0xfffceffe
SCPD0: 0x00000200
IER: 0x00028053
IIR: 0x00000000
IMR: 0xfffd73ae
ISR: 0x00000000
EIR: 0x00000000
EMR: 0xffffffed
ESR: 0x00000001
INST_PM: 0x00000800
ECOSKPD: 0x00000306
DCC: 0x000f0400 (single channel, XOR randomization: disabled, XOR bit: 11)
CHDECMISC: 0x22b97420 (XOR bank/rank, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
C0DRB0: 0x000f0400 (0x0400)
C0DRB1: 0x0000000f (0x000f)
C0DRB2: 0x00000000 (0x0000)
C0DRB3: 0x01080000 (0x0000)
C1DRB0: 0x0e0d0d0c (0x0d0c)
C1DRB1: 0x0f0e0e0d (0x0e0d)
C1DRB2: 0x100f0f0e (0x0f0e)
C1DRB3: 0x0e0d100f (0x100f)
C0DRA01: 0x04020108 (0x0108)
C0DRA23: 0x00000402 (0x0402)
C1DRA01: 0x100f0e0d (0x0e0d)
C1DRA23: 0x1211100f (0x100f)
PGETBL_CTL: 0x7ffc0001
VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
DPLL_TEST: 0x00010001 ()
CACHE_MODE_0: 0x00006820
D_STATE: 0x0000000b
DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
RENCLK_GATE_D1: 0x00000000
RENCLK_GATE_D2: 0x00000000
SDVOB: 0x00480004 (disabled, pipe A, stall disabled, detected)
SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected)
SDVOUDI: 0x00000000
DSPARB: 0x00001d9c
DSPFW1: 0x00000000
DSPFW2: 0x00000000
DSPFW3: 0x00000000
ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
LVDS: 0xc0308300 (enabled, pipe B, 18 bit, 1 channel)
DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
DVOB: 0x00480004 (disabled, pipe A, no stall, -hsync, -vsync)
DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
DVOA_SRCDIM: 0x00000000
DVOB_SRCDIM: 0x00000000
DVOC_SRCDIM: 0x00000000
PP_CONTROL: 0xabcd0001 (power target: on)
PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
PP_ON_DELAYS: 0x012c07d0
PP_OFF_DELAYS: 0x00fa07d0
PP_DIVISOR: 0x00270f05
PFIT_CONTROL: 0x00000000
PFIT_PGM_RATIOS: 0x99909990
PORT_HOTPLUG_EN: 0x00000220
PORT_HOTPLUG_STAT: 0x00000400
DSPACNTR: 0xd9000000 (enabled, pipe B)
DSPASTRIDE: 0x00002000 (8192 bytes)
DSPAPOS: 0x00000000 (0, 0)
DSPASIZE: 0x01df027f (640, 480)
DSPABASE: 0x04800000
DSPASURF: 0x00000000
DSPATILEOFF: 0x00000000
PIPEACONF: 0x00000000 (disabled, single-wide)
PIPEASRC: 0x04ff03ff (1280, 1024)
PIPEASTAT: 0x00000000 (status:)
PIPEA_GMCH_DATA_M: 0x00000000
PIPEA_GMCH_DATA_N: 0x00000000
PIPEA_DP_LINK_M: 0x00000000
PIPEA_DP_LINK_N: 0x00000000
CURSOR_A_BASE: 0x00000000
CURSOR_A_CONTROL: 0x00000000
CURSOR_A_POSITION: 0x00000000
FPA0: 0x00020f03 (n = 2, m1 = 15, m2 = 3)
FPA1: 0x00020f03 (n = 2, m1 = 15, m2 = 3)
DPLL_A: 0x14020003 (disabled, non-dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10, SDVO mult 1)
DPLL_A_MD: 0x00000000
HTOTAL_A: 0x06af04ff (1280 active, 1712 total)
HBLANK_A: 0x06af04ff (1280 start, 1712 end)
HSYNC_A: 0x05d70557 (1368 start, 1496 end)
VTOTAL_A: 0x044f03ff (1024 active, 1104 total)
VBLANK_A: 0x044f03ff (1024 start, 1104 end)
VSYNC_A: 0x04090402 (1027 start, 1034 end)
BCLRPAT_A: 0x00000000
VSYNCSHIFT_A: 0x00000000
DSPBCNTR: 0x58000000 (disabled, pipe A)
DSPBSTRIDE: 0x00001400 (5120 bytes)
DSPBPOS: 0x00000000 (0, 0)
DSPBSIZE: 0x03ff04ff (1280, 1024)
DSPBBASE: 0x07620000
DSPBSURF: 0x00000000
DSPBTILEOFF: 0x00000000
PIPEBCONF: 0x80000000 (enabled, single-wide)
PIPEBSRC: 0x027f01df (640, 480)
PIPEBSTAT: 0x00000302 (status: VSYNC_INT_STATUS DLINE_COMPARE_STATUS VBLANK_INT_STATUS)
PIPEB_GMCH_DATA_M: 0x00000000
PIPEB_GMCH_DATA_N: 0x00000000
PIPEB_DP_LINK_M: 0x00000000
PIPEB_DP_LINK_N: 0x00000000
CURSOR_B_BASE: 0x00000000
CURSOR_B_CONTROL: 0x10000000
CURSOR_B_POSITION: 0x008c0239
FPB0: 0x00031104 (n = 3, m1 = 17, m2 = 4)
FPB1: 0x00031104 (n = 3, m1 = 17, m2 = 4)
DPLL_B: 0x98026000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 2, p2 = 14, SDVO mult 1)
DPLL_B_MD: 0x00000000
HTOTAL_B: 0x058a0429 (1066 active, 1419 total)
HBLANK_B: 0x05200495 (1174 start, 1313 end)
HSYNC_B: 0x04eb04cb (1228 start, 1260 end)
VTOTAL_B: 0x032f031f (800 active, 816 total)
VBLANK_B: 0x032f031f (800 start, 816 end)
VSYNC_B: 0x03280322 (803 start, 809 end)
BCLRPAT_B: 0x00000000
VSYNCSHIFT_B: 0x00000000
VCLK_DIVISOR_VGA0: 0x00031108
VCLK_DIVISOR_VGA1: 0x00031406
VCLK_POST_DIV: 0x00020002
VGACNTRL: 0x80000000 (disabled)
TV_CTL: 0x000c0000
TV_DAC: 0x70000000
TV_CSC_Y: 0x0332012d
TV_CSC_Y2: 0x07d30104
TV_CSC_U: 0x0733052d
TV_CSC_U2: 0x05c70200
TV_CSC_V: 0x0340030c
TV_CSC_V2: 0x06d00200
TV_CLR_KNOBS: 0x00606000
TV_CLR_LEVEL: 0x010b00e1
TV_H_CTL_1: 0x00400359
TV_H_CTL_2: 0x80480022
TV_H_CTL_3: 0x007c0344
TV_V_CTL_1: 0x00f01415
TV_V_CTL_2: 0x00060607
TV_V_CTL_3: 0x80120001
TV_V_CTL_4: 0x000900f0
TV_V_CTL_5: 0x000a00f0
TV_V_CTL_6: 0x000900f0
TV_V_CTL_7: 0x000a00f0
TV_SC_CTL_1: 0xc1710087
TV_SC_CTL_2: 0x6b405140
TV_SC_CTL_3: 0x00000000
TV_WIN_POS: 0x00360024
TV_WIN_SIZE: 0x02640198
TV_FILTER_CTL_1: 0x800010bb
TV_FILTER_CTL_2: 0x00028283
TV_FILTER_CTL_3: 0x00014141
TV_CC_CONTROL: 0x00000000
TV_CC_DATA: 0x00000000
TV_H_LUMA_0: 0xb1403000
TV_H_LUMA_59: 0x0000b060
TV_H_CHROMA_0: 0xb1403000
TV_H_CHROMA_59: 0x0000b060
FBC_CFB_BASE: 0x00000000
FBC_LL_BASE: 0x00000000
FBC_CONTROL: 0x00000000
FBC_COMMAND: 0x00000000
FBC_STATUS: 0x20000000
FBC_CONTROL2: 0x00000000
FBC_FENCE_OFF: 0x00000000
FBC_MOD_NUM: 0x00000000
MI_MODE: 0x00000200
MI_ARB_STATE: 0x00000840
MI_RDRET_STATE: 0x00000000
ECOSKPD: 0x00000306
DP_B: 0x00000000
DPB_AUX_CH_CTL: 0x00000000
DPB_AUX_CH_DATA1: 0x00000000
DPB_AUX_CH_DATA2: 0x00000000
DPB_AUX_CH_DATA3: 0x00000000
DPB_AUX_CH_DATA4: 0x00000000
DPB_AUX_CH_DATA5: 0x00000000
DP_C: 0x00000000
DPC_AUX_CH_CTL: 0x00000000
DPC_AUX_CH_DATA1: 0x00000000
DPC_AUX_CH_DATA2: 0x00000000
DPC_AUX_CH_DATA3: 0x00000000
DPC_AUX_CH_DATA4: 0x00000000
DPC_AUX_CH_DATA5: 0x00000000
DP_D: 0x00000000
DPD_AUX_CH_CTL: 0x00000000
DPD_AUX_CH_DATA1: 0x00000000
DPD_AUX_CH_DATA2: 0x00000000
DPD_AUX_CH_DATA3: 0x00000000
DPD_AUX_CH_DATA4: 0x00000000
DPD_AUX_CH_DATA5: 0x00000000
AUD_CONFIG: 0x00000000
AUD_HDMIW_STATUS: 0x00000000
AUD_CONV_CHCNT: 0x00000000
VIDEO_DIP_CTL: 0x00000000
AUD_PINW_CNTR: 0x00000000
AUD_CNTL_ST: 0x00000000
AUD_PIN_CAP: 0x00000000
AUD_PINW_CAP: 0x00000000
AUD_PINW_UNSOLRESP: 0x00000000
AUD_OUT_DIG_CNVT: 0x00000000
AUD_OUT_CWCAP: 0x00000000
AUD_GRP_CAP: 0x00000000
FENCE 0: 0x00800341 (enabled, X tiled, 8192 pitch, 0x00800000 - 0x01000000 (8192kb))
FENCE 1: 0x04000231 (enabled, X tiled, 4096 pitch, 0x04000000 - 0x04400000 (4096kb))
FENCE 2: 0x00000000 (disabled)
FENCE 3: 0x09200131 (enabled, X tiled, 4096 pitch, 0x09200000 - 0x09400000 (2048kb))
FENCE 4: 0x0ba00131 (enabled, X tiled, 4096 pitch, 0x0ba00000 - 0x0bc00000 (2048kb))
FENCE 5: 0x0c800341 (enabled, X tiled, 8192 pitch, 0x0c800000 - 0x0d000000 (8192kb))
FENCE 6: 0x00000000 (disabled)
FENCE 7: 0x04800341 (enabled, X tiled, 8192 pitch, 0x04800000 - 0x05000000 (8192kb))
FENCE 8: 0x0a400131 (enabled, X tiled, 4096 pitch, 0x0a400000 - 0x0a600000 (2048kb))
FENCE 9: 0x08800121 (enabled, X tiled, 2048 pitch, 0x08800000 - 0x08a00000 (2048kb))
FENCE 10: 0x05600021 (enabled, X tiled, 2048 pitch, 0x05600000 - 0x05700000 (1024kb))
FENCE 11: 0x00000000 (disabled)
FENCE 12: 0x01000341 (enabled, X tiled, 8192 pitch, 0x01000000 - 0x01800000 (8192kb))
FENCE 13: 0x08000121 (enabled, X tiled, 2048 pitch, 0x08000000 - 0x08200000 (2048kb))
FENCE 14: 0x06200131 (enabled, X tiled, 4096 pitch, 0x06200000 - 0x06400000 (2048kb))
FENCE 15: 0x00000000 (disabled)
FENCE START 0: 0x0a400131 (disabled)
FENCE END 0: 0x08800121 (disabled)
FENCE START 1: 0x05600021 (disabled)
FENCE END 1: 0x00000000 (disabled)
FENCE START 2: 0x01000341 (disabled)
FENCE END 2: 0x08000121 (disabled)
FENCE START 3: 0x06200131 (disabled)
FENCE END 3: 0x00000000 (disabled)
FENCE START 4: 0x00000000 (disabled)
FENCE END 4: 0x00000000 (disabled)
FENCE START 5: 0x00000000 (disabled)
FENCE END 5: 0x00000000 (disabled)
FENCE START 6: 0x00000000 (disabled)
FENCE END 6: 0x00000000 (disabled)
FENCE START 7: 0x00000000 (disabled)
FENCE END 7: 0x00000000 (disabled)
FENCE START 8: 0x00000000 (disabled)
FENCE END 8: 0x00000000 (disabled)
FENCE START 9: 0x00000000 (disabled)
FENCE END 9: 0x00000000 (disabled)
FENCE START 10: 0x00000000 (disabled)
FENCE END 10: 0x00000000 (disabled)
FENCE START 11: 0x00000000 (disabled)
FENCE END 11: 0x00000000 (disabled)
FENCE START 12: 0x00000000 (disabled)
FENCE END 12: 0x00000000 (disabled)
FENCE START 13: 0x00000000 (disabled)
FENCE END 13: 0x00000000 (disabled)
FENCE START 14: 0x00000000 (disabled)
FENCE END 14: 0x00000000 (disabled)
FENCE START 15: 0x00000000 (disabled)
FENCE END 15: 0x00000000 (disabled)
INST_PM: 0x00000800
pipe A dot 108000 n 2 m1 15 m2 3 p1 2 p2 10
pipe B dot 72142 n 3 m1 17 m2 4 p1 2 p2 14
-------------- next part --------------
Screen 0: minimum 320 x 200, current 1280 x 800, maximum 4096 x 4096
LVDS1 connected 640x480+0+0 (normal left inverted right x axis y axis) 261mm x 163mm
1280x800 59.8 +
1024x768 60.0
800x600 60.3 56.2
640x480 59.9*
VGA1 disconnected (normal left inverted right x axis y axis)
DVI1 disconnected (normal left inverted right x axis y axis)
TV1 disconnected (normal left inverted right x axis y axis)
-------------- next part --------------
PGETBL_CTL: 0x7ffc0001
PGTBL_ER: 0x00000000
EXCC: 0x00000000
HWS_PGA: 0x362a9000
IPEIR: 0x00000000
IPEHR: 0x01000000
INST_DONE: 0x7fffffc0
NOPID: 0x00000000
HWSTAM: 0xfffceffe
SCPD0: 0x00000200
IER: 0x00028053
IIR: 0x00000000
IMR: 0xfffd73ae
ISR: 0x00000000
EIR: 0x00000000
EMR: 0xffffffed
ESR: 0x00000001
INST_PM: 0x00000800
ECOSKPD: 0x00000306
DCC: 0x000f0400 (single channel, XOR randomization: disabled, XOR bit: 11)
CHDECMISC: 0x22b97420 (XOR bank/rank, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
C0DRB0: 0x000f0400 (0x0400)
C0DRB1: 0x0000000f (0x000f)
C0DRB2: 0x00000000 (0x0000)
C0DRB3: 0x01080000 (0x0000)
C1DRB0: 0x0e0d0d0c (0x0d0c)
C1DRB1: 0x0f0e0e0d (0x0e0d)
C1DRB2: 0x100f0f0e (0x0f0e)
C1DRB3: 0x0e0d100f (0x100f)
C0DRA01: 0x04020108 (0x0108)
C0DRA23: 0x00000402 (0x0402)
C1DRA01: 0x100f0e0d (0x0e0d)
C1DRA23: 0x1211100f (0x100f)
PGETBL_CTL: 0x7ffc0001
VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
DPLL_TEST: 0x00010001 ()
CACHE_MODE_0: 0x00006820
D_STATE: 0x0000000b
DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
RENCLK_GATE_D1: 0x00000000
RENCLK_GATE_D2: 0x00000000
SDVOB: 0x00480004 (disabled, pipe A, stall disabled, detected)
SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected)
SDVOUDI: 0x00000000
DSPARB: 0x00001d9c
DSPFW1: 0x00000000
DSPFW2: 0x00000000
DSPFW3: 0x00000000
ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
LVDS: 0xc0308300 (enabled, pipe B, 18 bit, 1 channel)
DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
DVOB: 0x00480004 (disabled, pipe A, no stall, -hsync, -vsync)
DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
DVOA_SRCDIM: 0x00000000
DVOB_SRCDIM: 0x00000000
DVOC_SRCDIM: 0x00000000
PP_CONTROL: 0xabcd0001 (power target: on)
PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
PP_ON_DELAYS: 0x012c07d0
PP_OFF_DELAYS: 0x00fa07d0
PP_DIVISOR: 0x00270f05
PFIT_CONTROL: 0x80000448
PFIT_PGM_RATIOS: 0x99909990
PORT_HOTPLUG_EN: 0x00000220
PORT_HOTPLUG_STAT: 0x00000400
DSPACNTR: 0xd9000000 (enabled, pipe B)
DSPASTRIDE: 0x00002000 (8192 bytes)
DSPAPOS: 0x00000000 (0, 0)
DSPASIZE: 0x01df027f (640, 480)
DSPABASE: 0x00800000
DSPASURF: 0x00000000
DSPATILEOFF: 0x00000000
PIPEACONF: 0x00000000 (disabled, single-wide)
PIPEASRC: 0x04ff03ff (1280, 1024)
PIPEASTAT: 0x00000000 (status:)
PIPEA_GMCH_DATA_M: 0x00000000
PIPEA_GMCH_DATA_N: 0x00000000
PIPEA_DP_LINK_M: 0x00000000
PIPEA_DP_LINK_N: 0x00000000
CURSOR_A_BASE: 0x00000000
CURSOR_A_CONTROL: 0x00000000
CURSOR_A_POSITION: 0x00000000
FPA0: 0x00020e08 (n = 2, m1 = 14, m2 = 8)
FPA1: 0x00020e08 (n = 2, m1 = 14, m2 = 8)
DPLL_A: 0x14020003 (disabled, non-dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10, SDVO mult 1)
DPLL_A_MD: 0x00000000
HTOTAL_A: 0x06af04ff (1280 active, 1712 total)
HBLANK_A: 0x06af04ff (1280 start, 1712 end)
HSYNC_A: 0x05d70557 (1368 start, 1496 end)
VTOTAL_A: 0x044f03ff (1024 active, 1104 total)
VBLANK_A: 0x044f03ff (1024 start, 1104 end)
VSYNC_A: 0x04090402 (1027 start, 1034 end)
BCLRPAT_A: 0x00000000
VSYNCSHIFT_A: 0x00000000
DSPBCNTR: 0x58000000 (disabled, pipe A)
DSPBSTRIDE: 0x00001400 (5120 bytes)
DSPBPOS: 0x00000000 (0, 0)
DSPBSIZE: 0x03ff04ff (1280, 1024)
DSPBBASE: 0x05040000
DSPBSURF: 0x00000000
DSPBTILEOFF: 0x00000000
PIPEBCONF: 0x80000000 (enabled, single-wide)
PIPEBSRC: 0x027f01df (640, 480)
PIPEBSTAT: 0x00000302 (status: VSYNC_INT_STATUS DLINE_COMPARE_STATUS VBLANK_INT_STATUS)
PIPEB_GMCH_DATA_M: 0x00000000
PIPEB_GMCH_DATA_N: 0x00000000
PIPEB_DP_LINK_M: 0x00000000
PIPEB_DP_LINK_N: 0x00000000
CURSOR_B_BASE: 0x00000000
CURSOR_B_CONTROL: 0x10000000
CURSOR_B_POSITION: 0x00e5025f
FPB0: 0x00031009 (n = 3, m1 = 16, m2 = 9)
FPB1: 0x00031009 (n = 3, m1 = 16, m2 = 9)
DPLL_B: 0x98026000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 2, p2 = 14, SDVO mult 1)
DPLL_B_MD: 0x00000000
HTOTAL_B: 0x058a0429 (1066 active, 1419 total)
HBLANK_B: 0x05200495 (1174 start, 1313 end)
HSYNC_B: 0x04eb04cb (1228 start, 1260 end)
VTOTAL_B: 0x032f031f (800 active, 816 total)
VBLANK_B: 0x032f031f (800 start, 816 end)
VSYNC_B: 0x03280322 (803 start, 809 end)
BCLRPAT_B: 0x00000000
VSYNCSHIFT_B: 0x00000000
VCLK_DIVISOR_VGA0: 0x00031108
VCLK_DIVISOR_VGA1: 0x00031406
VCLK_POST_DIV: 0x00020002
VGACNTRL: 0x80000000 (disabled)
TV_CTL: 0x000c0000
TV_DAC: 0x70000000
TV_CSC_Y: 0x0332012d
TV_CSC_Y2: 0x07d30104
TV_CSC_U: 0x0733052d
TV_CSC_U2: 0x05c70200
TV_CSC_V: 0x0340030c
TV_CSC_V2: 0x06d00200
TV_CLR_KNOBS: 0x00606000
TV_CLR_LEVEL: 0x010b00e1
TV_H_CTL_1: 0x00400359
TV_H_CTL_2: 0x80480022
TV_H_CTL_3: 0x007c0344
TV_V_CTL_1: 0x00f01415
TV_V_CTL_2: 0x00060607
TV_V_CTL_3: 0x80120001
TV_V_CTL_4: 0x000900f0
TV_V_CTL_5: 0x000a00f0
TV_V_CTL_6: 0x000900f0
TV_V_CTL_7: 0x000a00f0
TV_SC_CTL_1: 0xc1710087
TV_SC_CTL_2: 0x6b405140
TV_SC_CTL_3: 0x00000000
TV_WIN_POS: 0x00360024
TV_WIN_SIZE: 0x02640198
TV_FILTER_CTL_1: 0x800010bb
TV_FILTER_CTL_2: 0x00028283
TV_FILTER_CTL_3: 0x00014141
TV_CC_CONTROL: 0x00000000
TV_CC_DATA: 0x00000000
TV_H_LUMA_0: 0xb1403000
TV_H_LUMA_59: 0x0000b060
TV_H_CHROMA_0: 0xb1403000
TV_H_CHROMA_59: 0x0000b060
FBC_CFB_BASE: 0x00000000
FBC_LL_BASE: 0x00000000
FBC_CONTROL: 0x00000000
FBC_COMMAND: 0x00000000
FBC_STATUS: 0x20000000
FBC_CONTROL2: 0x00000000
FBC_FENCE_OFF: 0x00000000
FBC_MOD_NUM: 0x00000000
MI_MODE: 0x00000200
MI_ARB_STATE: 0x00000840
MI_RDRET_STATE: 0x00000000
ECOSKPD: 0x00000306
DP_B: 0x00000000
DPB_AUX_CH_CTL: 0x00000000
DPB_AUX_CH_DATA1: 0x00000000
DPB_AUX_CH_DATA2: 0x00000000
DPB_AUX_CH_DATA3: 0x00000000
DPB_AUX_CH_DATA4: 0x00000000
DPB_AUX_CH_DATA5: 0x00000000
DP_C: 0x00000000
DPC_AUX_CH_CTL: 0x00000000
DPC_AUX_CH_DATA1: 0x00000000
DPC_AUX_CH_DATA2: 0x00000000
DPC_AUX_CH_DATA3: 0x00000000
DPC_AUX_CH_DATA4: 0x00000000
DPC_AUX_CH_DATA5: 0x00000000
DP_D: 0x00000000
DPD_AUX_CH_CTL: 0x00000000
DPD_AUX_CH_DATA1: 0x00000000
DPD_AUX_CH_DATA2: 0x00000000
DPD_AUX_CH_DATA3: 0x00000000
DPD_AUX_CH_DATA4: 0x00000000
DPD_AUX_CH_DATA5: 0x00000000
AUD_CONFIG: 0x00000000
AUD_HDMIW_STATUS: 0x00000000
AUD_CONV_CHCNT: 0x00000000
VIDEO_DIP_CTL: 0x00000000
AUD_PINW_CNTR: 0x00000000
AUD_CNTL_ST: 0x00000000
AUD_PIN_CAP: 0x00000000
AUD_PINW_CAP: 0x00000000
AUD_PINW_UNSOLRESP: 0x00000000
AUD_OUT_DIG_CNVT: 0x00000000
AUD_OUT_CWCAP: 0x00000000
AUD_GRP_CAP: 0x00000000
FENCE 0: 0x00800341 (enabled, X tiled, 8192 pitch, 0x00800000 - 0x01000000 (8192kb))
FENCE 1: 0x0a000131 (enabled, X tiled, 4096 pitch, 0x0a000000 - 0x0a200000 (2048kb))
FENCE 2: 0x00000000 (disabled)
FENCE 3: 0x06e00131 (enabled, X tiled, 4096 pitch, 0x06e00000 - 0x07000000 (2048kb))
FENCE 4: 0x03000341 (enabled, X tiled, 8192 pitch, 0x03000000 - 0x03800000 (8192kb))
FENCE 5: 0x04000231 (enabled, X tiled, 4096 pitch, 0x04000000 - 0x04400000 (4096kb))
FENCE 6: 0x0e500021 (enabled, X tiled, 2048 pitch, 0x0e500000 - 0x0e600000 (1024kb))
FENCE 7: 0x06000341 (enabled, X tiled, 8192 pitch, 0x06000000 - 0x06800000 (8192kb))
FENCE 8: 0x01800341 (enabled, X tiled, 8192 pitch, 0x01800000 - 0x02000000 (8192kb))
FENCE 9: 0x07a00121 (enabled, X tiled, 2048 pitch, 0x07a00000 - 0x07c00000 (2048kb))
FENCE 10: 0x0de00131 (enabled, X tiled, 4096 pitch, 0x0de00000 - 0x0e000000 (2048kb))
FENCE 11: 0x00000000 (disabled)
FENCE 12: 0x00000000 (disabled)
FENCE 13: 0x07e00121 (enabled, X tiled, 2048 pitch, 0x07e00000 - 0x08000000 (2048kb))
FENCE 14: 0x0b600121 (enabled, X tiled, 2048 pitch, 0x0b600000 - 0x0b800000 (2048kb))
FENCE 15: 0x0da00131 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 0: 0x01800341 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 0: 0x07a00121 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 1: 0x0de00131 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 1: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 2: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 2: 0x07e00121 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 3: 0x0b600121 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 3: 0x0da00131 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 4: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 4: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 5: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 5: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 6: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 6: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 7: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 7: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 8: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 8: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 9: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 9: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 10: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 10: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 11: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 11: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 12: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 12: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 13: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 13: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 14: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 14: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE START 15: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
FENCE END 15: 0x00000000 (enabled, X tiled, 4096 pitch, 0x0da00000 - 0x0dc00000 (2048kb))
INST_PM: 0x00000800
pipe A dot 108000 n 2 m1 14 m2 8 p1 2 p2 10
pipe B dot 72142 n 3 m1 16 m2 9 p1 2 p2 14
-------------- next part --------------
Screen 0: minimum 320 x 200, current 1280 x 800, maximum 4096 x 4096
LVDS1 connected 640x480+0+0 (normal left inverted right x axis y axis) 261mm x 163mm
1280x800 59.8 +
1024x768 60.0
800x600 60.3 56.2
640x480 59.9*
VGA1 disconnected (normal left inverted right x axis y axis)
DVI1 disconnected (normal left inverted right x axis y axis)
TV1 disconnected (normal left inverted right x axis y axis)
More information about the Intel-gfx
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