[Intel-gfx] [PATCH 19/26] drm/i915: DSPFW and BLC regs are in the display offset range

[Jesse Barnes]

On Fri, 08 Mar 2013 15:57:19 +0200
Jani Nikula <jani.nikula at linux.intel.com> wrote:

> 
> I also had this as a quick fix to the backlight access; it's also
> incomplete wrt the backlight registers.
> 
> --- a/drivers/gpu/drm/i915/intel_panel.c
> +++ b/drivers/gpu/drm/i915/intel_panel.c
> @@ -121,6 +121,9 @@ static int is_backlight_combination_mode(struct drm_device *dev)
>  {
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  
> +	if (IS_VALLEYVIEW(dev))
> +		return 0;
> +
>  	if (INTEL_INFO(dev)->gen >= 4)
>  		return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
>  
> @@ -338,12 +341,15 @@ void intel_panel_enable_backlight(struct drm_device *dev,
>  		if (tmp & BLM_PWM_ENABLE)
>  			goto set_level;
>  
> -		if (dev_priv->num_pipe == 3)
> -			tmp &= ~BLM_PIPE_SELECT_IVB;
> -		else
> -			tmp &= ~BLM_PIPE_SELECT;
> +		/* XXX: VLV per pipe registers */
> +		if (!IS_VALLEYVIEW(dev)) {
> +			if (dev_priv->num_pipe == 3)
> +				tmp &= ~BLM_PIPE_SELECT_IVB;
> +			else
> +				tmp &= ~BLM_PIPE_SELECT;
>  
> -		tmp |= BLM_PIPE(pipe);
> +			tmp |= BLM_PIPE(pipe);
> +		}
>  		tmp &= ~BLM_PWM_ENABLE;
>  
>  		I915_WRITE(reg, tmp);
> 

Ok I'll try that out, thanks.

-- 
Jesse Barnes, Intel Open Source Technology Center