[Intel-gfx] [PATCH 0/9] displayless PCH

[Ben Widawsky]

Certain fusing options allow customers to fuse off the South Display
which would result in hangs when reading/writing to those registers. In
addition, certain CPU display registers (like backlight) may actually
invoke writes to South Display.

This patch series enables our code to run displayless which can allow
the GEN hardware to be an offload GPU and not have a display hooked up.

This patch series hasn't been tested. A pre-cleaned version was tested,
and did work. I'm hoping Jeff (in the CC) can test this latest version.

patch 1: prep, could be separate
patch 2-7: Add some num_pipe == 0 checks
patch 8-9: Enable the actual platform we have

Ben Widawsky (9):
  drm/i915: Move num_pipes to intel info
  drm/i915: Support PCH no display
  drm/i915: PCH_NOP
  drm/i915: Don't touch South display when PCH_NOP
  drm/i915: Don't initialize watermark stuff with PCH_NOP
  drm/i915: PCH_NOP suspend/resume
  drm/i915: Don't wait for PCH on reset
  drm/i915: Set PCH_NOP
  drm/i915: Add a pipeless ivybridge configuration

 drivers/gpu/drm/i915/i915_dma.c      | 27 ++++++------
 drivers/gpu/drm/i915/i915_drv.c      | 79 +++++++++++++++++++++++++-----------
 drivers/gpu/drm/i915/i915_drv.h      |  6 ++-
 drivers/gpu/drm/i915/i915_gem.c      |  3 ++
 drivers/gpu/drm/i915/i915_irq.c      | 23 +++++++----
 drivers/gpu/drm/i915/i915_reg.h      |  1 +
 drivers/gpu/drm/i915/i915_suspend.c  | 57 ++++++++++++++++++--------
 drivers/gpu/drm/i915/intel_bios.c    |  3 ++
 drivers/gpu/drm/i915/intel_crt.c     |  3 ++
 drivers/gpu/drm/i915/intel_display.c | 33 +++++++++------
 drivers/gpu/drm/i915/intel_fb.c      |  5 ++-
 drivers/gpu/drm/i915/intel_i2c.c     |  4 +-
 drivers/gpu/drm/i915/intel_lvds.c    |  4 ++
 drivers/gpu/drm/i915/intel_overlay.c |  3 ++
 drivers/gpu/drm/i915/intel_panel.c   |  2 +-
 drivers/gpu/drm/i915/intel_pm.c      |  5 ++-
 16 files changed, 178 insertions(+), 80 deletions(-)

-- 
1.8.1.5