[Intel-gfx] [PATCH 06/15] drm/i915: there's no DSPSIZE register on gen4+

[Ben Widawsky]

On Fri, Mar 15, 2013 at 12:04:11PM -0700, Ben Widawsky wrote:
> On Thu, Mar 07, 2013 at 11:38:24AM +0200, Ville Syrjälä wrote:
> > On Wed, Mar 06, 2013 at 08:03:13PM -0300, Paulo Zanoni wrote:
> > > From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> > > 
> > > So don't read it when capturing the error state. This solves some
> > > "unclaimed register" messages on Haswell when we hang the GPU.
> > 
> > You're sure about gen4? I haven't really checked but my impression is
> > that gen4 is more like gen3, and gen4.5 more like gen5 as far as the
> > display is concerned (eg. gen4 would have the old video overlay, and
> > 4.5 would have video sprites). Can anyone confirm?
> 
> This register isn't anywhere in modern docs, what's up?

Ooops, inverted the logic in my head. If you make the check for gen <=6
which I can lazily check with modern docs:
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>

> 
> > 
> > > 
> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_display.c |    6 ++++--
> > >  1 file changed, 4 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > > index 789a95a..56cca6e 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -9348,7 +9348,8 @@ intel_display_capture_error_state(struct drm_device *dev)
> > >  
> > >  		error->plane[i].control = I915_READ(DSPCNTR(i));
> > >  		error->plane[i].stride = I915_READ(DSPSTRIDE(i));
> > > -		error->plane[i].size = I915_READ(DSPSIZE(i));
> > > +		if (INTEL_INFO(dev)->gen <= 3)
> > > +			error->plane[i].size = I915_READ(DSPSIZE(i));
> > >  		error->plane[i].pos = I915_READ(DSPPOS(i));
> > >  		error->plane[i].addr = I915_READ(DSPADDR(i));
> > >  		if (INTEL_INFO(dev)->gen >= 4) {
> > > @@ -9392,7 +9393,8 @@ intel_display_print_error_state(struct seq_file *m,
> > >  		seq_printf(m, "Plane [%d]:\n", i);
> > >  		seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
> > >  		seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
> > > -		seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
> > > +		if (INTEL_INFO(dev)->gen <= 3)
> > > +			seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
> > >  		seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
> > >  		seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
> > >  		if (INTEL_INFO(dev)->gen >= 4) {
> > > -- 
> > > 1.7.10.4
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx at lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > 
> > -- 
> > Ville Syrjälä
> > Intel OTC
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ben Widawsky, Intel Open Source Technology Center
> _______________________________________________
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> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ben Widawsky, Intel Open Source Technology Center