[Intel-gfx] [PATCH] drm/i915: Flush writes to GMBUS registers

[Chris Wilson]

On Mon, Mar 18, 2013 at 12:51:45PM +0100, Jiri Kosina wrote:
> On Mon, 18 Mar 2013, Chris Wilson wrote:
> 
> > If we do not complete the writes to the GMBUS registers, they remain
> > active for an indefinite period of time afterwards, even causing
> > spurious interrupts on gm45.
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > Link: http://lkml.kernel.org/r/alpine.LNX.2.00.1303151424140.9529@pobox.suse.cz
> > Cc: Shawn Starr <shawn.starr at rogers.com>
> > Cc: Jiri Kosina <jkosina at suse.cz>
> > Cc: Daniel Vetter <daniel.vetter at ffwll.ch>
> 
> Unfortunately I can't provide my Tested-by or Acked-by for this, as I am 
> still seeing the "nobody cared" for irq 16 with this patch applied.

The message reappeared on the third reboot. Perhaps an indicator that it
is a timing issue. I guess the sensible approach then is to exclude gen4
from the whitelist for gmbus irqs.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre