[Intel-gfx] [PATCH 2/4] drm/i915: HSW PM Cleaning - Removing unecessary register/bits set.

[Rodrigo Vivi]

According to HSW PM Programming guide it is not needed touch this registers
or setting these values anymore.

CC: Zanoni <paulo.r.zanoni at intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 27f94cd..aea5fac 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2566,9 +2566,13 @@ static void gen6_enable_rps(struct drm_device *dev)
 	/* disable the counters and set deterministic thresholds */
 	I915_WRITE(GEN6_RC_CONTROL, 0);
 
-	I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
-	I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
-	I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
+	if (IS_HASWELL(dev))
+		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
+	else {
+		I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
+		I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
+		I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
+	}
 	I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
 	I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
 
@@ -2576,10 +2580,13 @@ static void gen6_enable_rps(struct drm_device *dev)
 		I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
 
 	I915_WRITE(GEN6_RC_SLEEP, 0);
-	I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
+	if (!IS_HASWELL(dev))
+		I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
 	I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
-	I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
-	I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
+	if (!IS_HASWELL(dev)) {
+		I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
+		I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
+	}
 
 	/* Check if we are enabling RC6 */
 	rc6_mode = intel_enable_rc6(dev_priv->dev);
-- 
1.8.1.4