[Intel-gfx] [PATCH 11/13] drm/i915: clean up plane bpp confusion

[Jesse Barnes]

On Wed, 27 Mar 2013 00:45:00 +0100
Daniel Vetter <daniel.vetter at ffwll.ch> wrote:

> - There is no 16bpc linear color format in our hw. gen4+ has a 16 bpc
>   float layout, but we don't really support it.
> - 10bpc is a gen4+ feature, fix up the support for it.
> - Update_plane should never see a wrong fb bpp value, BUG in the
>   corresponding cases.
> 
> v2: Rebase on top of Ville's plane pixel layout changes.
> 
> v3: Actually drop the old gen4 check for 10bpc planes, spotted
> by Ville Syrjälä.
> 
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 20 ++++++++------------
>  1 file changed, 8 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 51557ba..bbf31aa 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2096,8 +2096,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
>  		dspcntr |= DISPPLANE_RGBX101010;
>  		break;
>  	default:
> -		DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
> -		return -EINVAL;
> +		BUG();
>  	}
>  
>  	if (INTEL_INFO(dev)->gen >= 4) {
> @@ -2190,8 +2189,7 @@ static int ironlake_update_plane(struct drm_crtc *crtc,
>  		dspcntr |= DISPPLANE_RGBX101010;
>  		break;
>  	default:
> -		DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
> -		return -EINVAL;
> +		BUG();
>  	}
>  
>  	if (obj->tiling_mode != I915_TILING_NONE)
> @@ -7372,21 +7370,19 @@ pipe_config_set_bpp(struct drm_crtc *crtc,
>  		bpp = 8*3;
>  		break;
>  	case 30:
> +		if (INTEL_INFO(dev)->gen < 4) {
> +			DRM_DEBUG_KMS("10 bpc not supported on gen2/3\n");
> +			return -EINVAL;
> +		}
> +
>  		bpp = 10*3;
>  		break;
> -	case 48:
> -		bpp = 12*3;
> -		break;
> +	/* TODO: gen4+ supports 16 bpc floating point, too. */
>  	default:
>  		DRM_DEBUG_KMS("unsupported depth\n");
>  		return -EINVAL;
>  	}
>  
> -	if (fb->depth > 24 && !HAS_PCH_SPLIT(dev)) {
> -		DRM_DEBUG_KMS("high depth not supported on gmch platforms\n");
> -		return -EINVAL;
> -	}
> -
>  	pipe_config->pipe_bpp = bpp;
>  
>  	/* Clamp display bpp to EDID value */

You don't want to squash this into 8/13?  It looks ok.

Sorry about the 48; it's 16:16:16:16 ignoring alpha, so you end up with
48bpp and my backwards calc for bpc ignored alpha again and ended up at
12. :)

Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center