[Intel-gfx] [PATCH 6/9] drm/i915: make intel_ddi_get_cdclk_freq return values in KHz

[Paulo Zanoni]

2013/5/5 Chris Wilson <chris at chris-wilson.co.uk>:
> On Fri, May 03, 2013 at 05:23:42PM -0300, Paulo Zanoni wrote:
>> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>>
>> With this, that 338 can finally become the correct 337500.
>>
>> Due to the change we need to adjust the intel_dp_aux_ch function to
>> set the correct value, so adjust the division and also use
>> DIV_ROUND_CLOSEST instead of the old "round down" behavior because the
>> spec says the value "should be programmed to get as close as possible
>> to the ideal rate of 2MHz".
>
> Can you please demonstrate an instance where this code produces a
> different value? And only then correct the constants.

I use the 337500 value on the next patch, when setting the
ips_linetime value. The correct frequency is 337500, not 338000.

ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
intel_ddi_get_cdclk_freq);
For a mode with htotal of 2640 [0] we'll have: (i) (2640 * 1000 * 8) /
338000 = 62.48, resulting in 62 and (ii) (2640 * 1000 * 8) / 337500 =
62.57 resulting in 63.

For the case inside intel_dp.c:
Previously we were using 338. So with the old formula we were writing
338/2 = 169 to the register. And 337500 / 169 = 1997.04 (we use 337500
here because it's the real clock value). With the new value of
337500/2000 we'll have 168.75, which is 168 on the round-down case and
169 on the round-closest case. If we write 168 to the register, 337500
/ 168 = 2008.92, and 2008.92 is more distant from 2000 than 1997.04.
So with this patch we're changing the formula but still writing the
same correct value to the DP AUX register.

[0]: That's 1920x1080 at 50Hz on my DP monitor.

> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre



-- 
Paulo Zanoni