[Intel-gfx] [PATCH 4/7] drm/i915: rip out TV-out lore ...

[Jani Nikula]

On Tue, 30 Apr 2013, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> This seems to be an impressive piece of copy&pasta lore. I've
> checked all docs and on most platforms these bits are all MBZ, with
> the exception of the SDVO pixel multiplier on gen3. On gen4 that
> moved to a special DPLL_MD registers.
>
> No indication whatsoever that we actually need this for native
> TV-out support. I suspect this started as a hack when we didn't
> yet have proper pixel multiplier support in place for SDVO TV, but
> then got stuck in a life of its own.
>
> Just rip it out.
>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 4 ----
>  1 file changed, 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 317e055..e68d26a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4548,10 +4548,6 @@ static void i9xx_update_pll(struct intel_crtc *crtc,
>  
>  	if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
>  		dpll |= PLL_REF_INPUT_TVCLKINBC;
> -	else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
> -		/* XXX: just matching BIOS for now */
> -		/*	dpll |= PLL_REF_INPUT_TVCLKINBC; */
> -		dpll |= 3;

I found a g45 spec saying this about bits 7:0 on CTG:

"FPB1 P1 Post Divisor: Writes to this byte cause the staging register
 contents to be written into the active register when in the VGA mode of
 operation. This will also occur when the VGA MSR register is written."

Additionally 3 is an illegal value...

Reviewed-by: Jani Nikula <jani.nikula at intel.com>


>  	else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
>  		 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
>  		dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
> -- 
> 1.7.11.7
>
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