[Intel-gfx] [PATCH] drm/i915: implement WADPOClockGatingDisable for LPT

[Daniel Vetter]

On Wed, May 08, 2013 at 01:54:17PM +0100, Damien Lespiau wrote:
> On Tue, May 07, 2013 at 03:40:21PM +0100, Damien Lespiau wrote:
> > On Tue, May 07, 2013 at 10:46:01AM -0300, Paulo Zanoni wrote:
> > > 2013/5/7 Damien Lespiau <damien.lespiau at intel.com>:
> > > > On Tue, May 07, 2013 at 02:10:05PM +0100, Damien Lespiau wrote:
> > > >> On Wed, Apr 17, 2013 at 06:15:49PM -0300, Paulo Zanoni wrote:
> > > >> > From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> > > >> >
> > > >> > This should prevent mode set failures on LPT.
> > > >> >
> > > >> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> > > >> > ---
> > > >> >  drivers/gpu/drm/i915/intel_pm.c |    5 +++++
> > > >> >  1 file changed, 5 insertions(+)
> > > >> >
> > > >> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > >> > index 413877d..15ff0ac 100644
> > > >> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > >> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > >> > @@ -3758,6 +3758,11 @@ static void lpt_init_clock_gating(struct drm_device *dev)
> > > >> >             I915_WRITE(SOUTH_DSPCLK_GATE_D,
> > > >> >                        I915_READ(SOUTH_DSPCLK_GATE_D) |
> > > >> >                        PCH_LP_PARTITION_LEVEL_DISABLE);
> > > >> > +
> > > >> > +   /* WADPOClockGatingDisable */
> > > >> > +   I915_WRITE(_TRANSA_CHICKEN1,
> > > >> > +              I915_READ(_TRANSA_CHICKEN1) |
> > > >> > +              TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
> 
> 
> Of course, It'd be good to add the :hsw at the end of
> WADPOClockGatingDisable (ammending the patch when applying?) now that
> the workaround documentation has been pushed.

Done and queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch