[Intel-gfx] [PATCH 2/4] drm/i915: merge VLV eDP and DP AUX clock divider calculation

Daniel Vetter daniel at ffwll.ch
Tue May 21 12:42:30 CEST 2013

On Tue, May 21, 2013 at 12:36 PM, Imre Deak <imre.deak at intel.com> wrote:
> On Tue, 2013-05-21 at 11:12 +0200, Daniel Vetter wrote:
>> On Thu, May 16, 2013 at 02:40:35PM +0300, Imre Deak wrote:
>> > On ValleyView for both eDP and DP the AUX input clock is 200MHz, so we
>> > can calculate for both the clock divider for the 2MHz target rate at the
>> > same place. Afterwards we can also replace the is_cpu_edp() check with a
>> > check for port A.
>> >
>> > Signed-off-by: Imre Deak <imre.deak at intel.com>
>> There's a now-dead IS_VLV case in intel_hrawclk which should be killed
>> with this patch, too.
> Shouldn't it still return the correct value if someone calls it in the
> future? Actually it's also used in
> intel_dp_init_panel_power_sequencer_registers().

Indeed. I think though it's better to make this an explicit vlv case
since hrawclk talks about the FSB. And that thing pretty surely
doesn't exist on vlv any more ;-) So maybe a follow-up patch?
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

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