[Intel-gfx] [PATCH 3/9] drm/i915: use the mode->htotal to calculate linetime watermarks

Daniel Vetter daniel at ffwll.ch
Tue May 21 16:59:48 CEST 2013


On Tue, May 21, 2013 at 4:33 PM, Paulo Zanoni <przanoni at gmail.com> wrote:
> 2013/5/21 Daniel Vetter <daniel at ffwll.ch>:
>> On Fri, May 03, 2013 at 05:23:39PM -0300, Paulo Zanoni wrote:
>>> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>>>
>>> ... instead of mode->crtc_display. The spec says "pipe horizontal
>>> total number of pixels" and the "Haswell Watermark Calculator" tool
>>> uses the "Pipe H Total" instead of "Pipe H Src" as the value.
>>>
>>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/intel_pm.c |    2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>>> index d056bc9..4cc5f99 100644
>>> --- a/drivers/gpu/drm/i915/intel_pm.c
>>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>>> @@ -2035,7 +2035,7 @@ haswell_update_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
>>>        * row at the given clock rate, multiplied by 8.
>>>        * */
>>>       temp |= PIPE_WM_LINETIME_TIME(
>>> -             ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
>>> +             ((mode->htotal * 1000) / mode->clock) * 8);
>>
>> Big question: What's the right value for interlaced modes? On progressive
>> mode crtc_ mode values match the non-crtc_ prefixed ones, but not so much
>> for interlaced modes ... So if your tool expects something resembling what
>> we program into the pipe registers, we need to change this again.
>>
>> Merged for now since the spec explicitly says "pixels", but I'd like
>> someone to double-check this.
>
> The WM calculator tool says:
> "Pipe H total is found in PIPE_HTOTAL horizontal field".
>
> But mode->htotal and mode->crtc_htotal are the same even when the mode
> is interlaced. So at least the values we compute are correct. I could
> write a follow-up patch updating this if you want.

Oh, I've mixed up the horizontal timings with the vertical ones.
You're right, everything is working correctly as-is.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch



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