[Intel-gfx] [PATCH v2 3/5] drm/i915: drop redundant warnings on not holding dpio_lock

[Jesse Barnes]

On Wed, 22 May 2013 15:36:18 +0300
Jani Nikula <jani.nikula at intel.com> wrote:

> The lower level sideband read/write functions already do this.
> 
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c   |    6 ------
>  drivers/gpu/drm/i915/intel_hdmi.c |    4 ----
>  2 files changed, 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3426a61..76d950e 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1442,8 +1442,6 @@ static void intel_pre_enable_dp(struct intel_encoder *encoder)
>  		int pipe = intel_crtc->pipe;
>  		u32 val;
>  
> -		WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
> -
>  		val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
>  		val = 0;
>  		if (pipe)
> @@ -1470,8 +1468,6 @@ static void intel_dp_pre_pll_enable(struct intel_encoder *encoder)
>  	if (!IS_VALLEYVIEW(dev))
>  		return;
>  
> -	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
> -
>  	/* Program Tx lane resets to default */
>  	intel_dpio_write(dev_priv, DPIO_PCS_TX(port),
>  			 DPIO_PCS_TX_LANE2_RESET |
> @@ -1622,8 +1618,6 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
>  	uint8_t train_set = intel_dp->train_set[0];
>  	int port = vlv_dport_to_channel(dport);
>  
> -	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
> -
>  	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
>  	case DP_TRAIN_PRE_EMPHASIS_0:
>  		preemph_reg_value = 0x0004000;
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 18f8ce0..83b63d7 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1018,8 +1018,6 @@ static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
>  	if (!IS_VALLEYVIEW(dev))
>  		return;
>  
> -	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
> -
>  	/* Enable clock channels for this port */
>  	val = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(port));
>  	val = 0;
> @@ -1063,8 +1061,6 @@ static void intel_hdmi_pre_pll_enable(struct intel_encoder *encoder)
>  	if (!IS_VALLEYVIEW(dev))
>  		return;
>  
> -	WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
> -
>  	/* Program Tx lane resets to default */
>  	intel_dpio_write(dev_priv, DPIO_PCS_TX(port),
>  			 DPIO_PCS_TX_LANE2_RESET |

Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>

-- 
Jesse Barnes, Intel Open Source Technology Center