[Intel-gfx] [PATCH 01/18] [v2] drm/i915: Comments for semaphore clarification

[Damien Lespiau]

On Tue, May 28, 2013 at 07:22:17PM -0700, Ben Widawsky wrote:
> Semaphores are tied very closely to the rings in the GPU. Trivial patch
> adds comments to the existing code so that when we add new rings we can
> include comments there as well. It also helps distinguish the ring to
> semaphore mailbox interactions by using the ringname in the semaphore
> data structures.
> 
> This patch should have no functional impact.
> 
> v2: The English parts (as opposed to register names) of the comments
> were reversed. (Damien)
> 
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>

Reviewed-by: Damien Lespiau <damien.lespiau at intel.com>

-- 
Damien

> ---
>  drivers/gpu/drm/i915/i915_reg.h         | 12 ++++++------
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++++++++---------
>  drivers/gpu/drm/i915/intel_ringbuffer.h |  4 ++--
>  3 files changed, 17 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dbd9de5..6579d0c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -265,12 +265,12 @@
>  #define  MI_SEMAPHORE_UPDATE	    (1<<21)
>  #define  MI_SEMAPHORE_COMPARE	    (1<<20)
>  #define  MI_SEMAPHORE_REGISTER	    (1<<18)
> -#define  MI_SEMAPHORE_SYNC_RV	    (2<<16)
> -#define  MI_SEMAPHORE_SYNC_RB	    (0<<16)
> -#define  MI_SEMAPHORE_SYNC_VR	    (0<<16)
> -#define  MI_SEMAPHORE_SYNC_VB	    (2<<16)
> -#define  MI_SEMAPHORE_SYNC_BR	    (2<<16)
> -#define  MI_SEMAPHORE_SYNC_BV	    (0<<16)
> +#define  MI_SEMAPHORE_SYNC_RB	    (0<<16) /* BCS wait for RCS  (BRSYNC) */
> +#define  MI_SEMAPHORE_SYNC_RV	    (2<<16) /* VCS wait for RCS  (VRSYNC) */
> +#define  MI_SEMAPHORE_SYNC_VR	    (0<<16) /* RCS wait for VCS  (RVSYNC) */
> +#define  MI_SEMAPHORE_SYNC_VB	    (2<<16) /* BCS wait for VCS  (BVSYNC) */
> +#define  MI_SEMAPHORE_SYNC_BV	    (0<<16) /* VCS wait for BCS  (VBSYNC) */
> +#define  MI_SEMAPHORE_SYNC_BR	    (2<<16) /* RCS wait for BCS  (RBSYNC) */
>  #define  MI_SEMAPHORE_SYNC_INVALID  (1<<0)
>  /*
>   * 3D instructions used by the kernel
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 9b97cf6..2d2a362 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1671,9 +1671,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
>  		ring->get_seqno = gen6_ring_get_seqno;
>  		ring->set_seqno = ring_set_seqno;
>  		ring->sync_to = gen6_ring_sync;
> -		ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID;
> -		ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV;
> -		ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB;
> +		ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
> +		ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
> +		ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
>  		ring->signal_mbox[0] = GEN6_VRSYNC;
>  		ring->signal_mbox[1] = GEN6_BRSYNC;
>  	} else if (IS_GEN5(dev)) {
> @@ -1830,9 +1830,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
>  		ring->irq_put = gen6_ring_put_irq;
>  		ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>  		ring->sync_to = gen6_ring_sync;
> -		ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR;
> -		ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID;
> -		ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB;
> +		ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
> +		ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
> +		ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
>  		ring->signal_mbox[0] = GEN6_RVSYNC;
>  		ring->signal_mbox[1] = GEN6_BVSYNC;
>  	} else {
> @@ -1876,9 +1876,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
>  	ring->irq_put = gen6_ring_put_irq;
>  	ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>  	ring->sync_to = gen6_ring_sync;
> -	ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR;
> -	ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV;
> -	ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID;
> +	ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
> +	ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
> +	ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
>  	ring->signal_mbox[0] = GEN6_RBSYNC;
>  	ring->signal_mbox[1] = GEN6_VBSYNC;
>  	ring->init = init_ring_common;
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index ef374a8..24268fb 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -105,8 +105,8 @@ struct  intel_ring_buffer {
>  	int		(*sync_to)(struct intel_ring_buffer *ring,
>  				   struct intel_ring_buffer *to,
>  				   u32 seqno);
> -
> -	u32		semaphore_register[3]; /*our mbox written by others */
> +	/* our mbox written by others */
> +	u32		semaphore_register[I915_NUM_RINGS];
>  	u32		signal_mbox[2]; /* mboxes this ring signals to */
>  	/**
>  	 * List of objects currently involved in rendering from the
> -- 
> 1.8.3
>