[Intel-gfx] [PATCH 1/4] drm/i915: add bunit read/write routines

[Ville Syrjälä]

On Fri, Nov 01, 2013 at 08:41:24AM -0700, Jesse Barnes wrote:
> For modifying self-refresh exit latency.
> 
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>

Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/i915_drv.h       |  2 ++
>  drivers/gpu/drm/i915/i915_reg.h       |  1 +
>  drivers/gpu/drm/i915/intel_sideband.c | 16 ++++++++++++++++
>  3 files changed, 19 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index cc40cbf..5edf9bb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2403,6 +2403,8 @@ u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
>  void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>  u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
>  void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> +u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
> +void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>  u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
>  void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>  u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index de58947..737d8a3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -349,6 +349,7 @@
>  #define   IOSF_BYTE_ENABLES_SHIFT		4
>  #define   IOSF_BAR_SHIFT			1
>  #define   IOSF_SB_BUSY				(1<<0)
> +#define   IOSF_PORT_BUNIT			0x3
>  #define   IOSF_PORT_PUNIT			0x4
>  #define   IOSF_PORT_NC				0x11
>  #define   IOSF_PORT_DPIO			0x12
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index 9944d81..d43e457 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -90,6 +90,22 @@ void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
>  	mutex_unlock(&dev_priv->dpio_lock);
>  }
>  
> +u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
> +{
> +	u32 val = 0;
> +
> +	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
> +			PUNIT_OPCODE_REG_READ, reg, &val);
> +
> +	return val;
> +}
> +
> +void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> +{
> +	vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
> +			PUNIT_OPCODE_REG_WRITE, reg, &val);
> +}
> +
>  u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
>  {
>  	u32 val = 0;
> -- 
> 1.8.3.1
> 
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-- 
Ville Syrjälä
Intel OTC