[Intel-gfx] [PATCH 1/2] drm/i915: Fix fbc + rc6 combination on SNB

[Chris Wilson]

On Fri, Nov 01, 2013 at 05:02:52PM -0700, Ben Widawsky wrote:
> On Sandybridge we must set the "PPGTT Render Target Base Address Valid
> for FBC" bit as noted in the programming guide. We did this at clock
> gating init. Thisbit is not saved and restored with RC6 power context,
> so the resetting it at ring flush should fix that.
> 
> The effect of not doing this should be corruption, and not a hang - as
> has so often been the case.
> 
> Note that we should actually clear this bit as well when not blitting to
> the scanout (using the blitter for other things), or else all operations

This needs to be enabled during the invalidate phase, so that the
tracking is active for the batch. However, the fbc_dirty flag is
currently set later.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre