[Intel-gfx] [PATCH 42/62] drm/i915/bdw: Implement WaSwitchSolVfFArbitrationPriority

[Ville Syrjälä]

On Sat, Nov 02, 2013 at 09:07:40PM -0700, Ben Widawsky wrote:
> GEN8 also needs this workaround.

Not according to the w/a database.

But the register description is the same for both HSW and BDW. Also for
HSW, the w/a doesn't actually say whether we should set or clear the bit.
the default is listed to be 0, so I guess we should set it, but then
it's unclear why BDW wouldn't need the w/a. Once again a very poorly
docuemnted w/a :(

> 
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index caf31b7..68dc363 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5192,6 +5192,9 @@ static void gen8_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(WM3_LP_ILK, 0);
>  	I915_WRITE(WM2_LP_ILK, 0);
>  	I915_WRITE(WM1_LP_ILK, 0);
> +
> +	/* WaSwitchSolVfFArbitrationPriority */
> +	I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>  }
>  
>  static void haswell_init_clock_gating(struct drm_device *dev)
> -- 
> 1.8.4.2
> 
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-- 
Ville Syrjälä
Intel OTC