[Intel-gfx] [PATCH 21/62] drm/i915/bdw: Support BDW caching

[Chris Wilson]

On Sat, Nov 02, 2013 at 09:07:19PM -0700, Ben Widawsky wrote:
> +static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv)
> +{
> +#define GEN8_PPAT_UC		(0<<0)
> +#define GEN8_PPAT_WC		(1<<0)
> +#define GEN8_PPAT_WT		(2<<0)
> +#define GEN8_PPAT_WB		(3<<0)
> +#define GEN8_PPAT_ELLC_OVERRIDE	(0<<2)
> +#define GEN8_PPAT_LLC		(1<<2)
> +#define GEN8_PPAT_LLCELLC	(2<<2)
> +#define GEN8_PPAT_LLCeLLC	(3<<2) /* BSPEC mistake? */
> +#define GEN8_PPAT_AGE(x)	(x<<4)
> +#define GEN8_PPAT(i, x) ((uint64_t) (x) << ((i) * 8))
> +	uint64_t pat;
> +
> +	pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
> +	      GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
> +	      GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
> +	      GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
> +	      GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
> +	      GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
> +	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
> +	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
> +
> +	I915_WRITE(GEN8_PRIVATE_PAT, pat);
> +	I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);

I915_WRITE64() or a scary-ass comment to explain why we cannot.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre