[Intel-gfx] [PATCH 14/62] drm/i915/bdw: dispatch updates (64b related)

[Paulo Zanoni]

2013/11/3 Ben Widawsky <benjamin.widawsky at intel.com>:
> The command to emit batch buffers has changed to address 48b addresses.
> It seemed reasonable that we could still use the old instruction where
> emitting 0 for length would do the right thing, but it seems to bother
> the simulator when the code does that.
>
> Now the second dword in the command has the upper 16b of the address of
> the batchbuffer.
>
> v2: Remove duplicated vfun assignment.
>
> v3: Squash in VECS support changes from Zhao Yakui <yakui.zhao at intel.com>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>

Looks like I was assigned to review this patch. I am not familiar with
this code at all, so please forgive my stupid questions.


> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 32 +++++++++++++++++++++++++++++---
>  1 file changed, 29 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index b2161f2..60ef8ff 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -1684,6 +1684,27 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
>  }
>
>  static int
> +gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
> +                             u32 offset, u32 len,
> +                             unsigned flags)
> +{
> +       int ret;
> +
> +       ret = intel_ring_begin(ring, 4);
> +       if (ret)
> +               return ret;
> +
> +       intel_ring_emit(ring, MI_BATCH_BUFFER_START | 1);

What about bit 8? The other distpatch_execbuffer functions seem to set
it conditionally based on the I915_DISPATCH_SECURE flag. Why do we
ignore it now?

Not a problem, just an observation: I also couldn't find a sign of the
existence of MI_BATCH_PPGTT_HSW: poor bit, survived for just 1 gen :(.


> +       /* bit0-7 is the length on GEN6+ */
> +       intel_ring_emit(ring, offset);
> +       intel_ring_emit(ring, 0);
> +       intel_ring_emit(ring, MI_NOOP);
> +       intel_ring_advance(ring);
> +
> +       return 0;
> +}
> +
> +static int
>  hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
>                               u32 offset, u32 len,
>                               unsigned flags)
> @@ -1822,6 +1843,8 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
>         ring->write_tail = ring_write_tail;
>         if (IS_HASWELL(dev))
>                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
> +       else if (IS_GEN8(dev))
> +               ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
>         else if (INTEL_INFO(dev)->gen >= 6)
>                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>         else if (INTEL_INFO(dev)->gen >= 4)
> @@ -1948,12 +1971,13 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
>                         ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT;
>                         ring->irq_get = gen8_ring_get_irq;
>                         ring->irq_put = gen8_ring_put_irq;
> +                       ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
>                 } else {
>                         ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
>                         ring->irq_get = gen6_ring_get_irq;
>                         ring->irq_put = gen6_ring_put_irq;
> +                       ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>                 }
> -               ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>                 ring->sync_to = gen6_ring_sync;
>                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
>                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
> @@ -2003,12 +2027,13 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
>                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
>                 ring->irq_get = gen8_ring_get_irq;
>                 ring->irq_put = gen8_ring_put_irq;
> +               ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
>         } else {
>                 ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
>                 ring->irq_get = gen6_ring_get_irq;
>                 ring->irq_put = gen6_ring_put_irq;
> +               ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>         }
> -       ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>         ring->sync_to = gen6_ring_sync;
>         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
>         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
> @@ -2037,7 +2062,6 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
>         ring->add_request = gen6_add_request;
>         ring->get_seqno = gen6_ring_get_seqno;
>         ring->set_seqno = ring_set_seqno;
> -       ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>
>         if (INTEL_INFO(dev)->gen >= 8) {
>                 ring->irq_enable_mask =
> @@ -2045,10 +2069,12 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev)
>                         GT_RENDER_CS_MASTER_ERROR_INTERRUPT;
>                 ring->irq_get = gen8_ring_get_irq;
>                 ring->irq_put = gen8_ring_put_irq;
> +               ring->dispatch_execbuffer = gen8_ring_dispatch_execbuffer;
>         } else {
>                 ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
>                 ring->irq_get = hsw_vebox_get_irq;
>                 ring->irq_put = hsw_vebox_put_irq;
> +               ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
>         }
>         ring->sync_to = gen6_ring_sync;
>         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
> --
> 1.8.4.2
>
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-- 
Paulo Zanoni