[Intel-gfx] [PATCH] [VPG HSW-A] drm/i915: BUN vol4g[DevHSW] Vblank interrupt on disabled pipe

[Ramakutty, SandeepX]

Hi Ville,

Thanks for the feedback.

The BUN indicates this as a workaround for hardware limitation. It specifies that if the interrupt is not disabled on a pipe that is disabled, the system will not go to C3 state. This affects situations when only edp is connected and hdmi is not connected. That is Pipe B is disabled.  Since this is generic for all haswell platforms not sure whether non Android systems goes to the C3 state if the BUN is not implemented.

Details can be found in North Display Engine Registers-> North Display Engine Shared Functions -> Interrupts 

Regards,
Sandeep

-----Original Message-----
From: Ville Syrjälä [mailto:ville.syrjala at linux.intel.com] 
Sent: Wednesday, September 04, 2013 6:16 PM
To: Ramakutty, SandeepX
Cc: intel-gfx at lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] [VPG HSW-A] drm/i915: BUN vol4g[DevHSW] Vblank interrupt on disabled pipe

On Wed, Sep 04, 2013 at 05:14:02PM +0530, Sandeep Ramankutty wrote:
> This change is to comply with the BUN - Vblank interrupt on disabled pipe.
> BUN states - Do not unmask and enable a vertical blank interrupt on a 
> pipe that is not enabled. Do not leave this interrupt enabled and 
> unmasked after the associated pipe is disabled. If the vblank 
> interrupt is unmasked and enabled on a disabled pipe it will block package C3, wasting power.

We mask the interrupt in IMR when we don't need it, but we do leave it enabled in IER. Is that a problem on HSW? I'm guessing not, since powertop is telling me that I'm currently reaching pc8 w/ displays off, and pc7 w/ eDP on.

In any case the patch would be buggy since it has no locking around DEIER RMW accesses. But since powertop is telling me everything is already fine, we shouldn't need this patch anyway.

--
Ville Syrjälä
Intel OTC