[Intel-gfx] [PATCH] drm/i915: Wrap the preallocated BIOS framebuffer and preserve for KMS fbcon v5
Jesse Barnes
jbarnes at virtuousgeek.org
Thu Nov 7 20:40:13 CET 2013
Retrieve current framebuffer config info from the regs and create an fb
object for the buffer the BIOS or boot loader left us. This should
allow for smooth transitions to userspace apps once we finish the
initial configuration construction.
v2: check for non-native modes and adjust (Jesse)
fixup aperture and cmap frees (Imre)
use unlocked unref if init_bios fails (Jesse)
fix curly brace around DSPADDR check (Imre)
comment failure path for pin_and_fence (Imre)
v3: fixup fixup of aperture frees (Chris)
v4: update to current bits (locking & pin_and_fence hack) (Jesse)
v5: move fb config fetch to display code (Jesse)
re-order hw state readout on initial load to suit fb inherit (Jesse)
re-add pin_and_fence in fbdev code to make sure we refcount properly (Jesse)
Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_dma.c | 4 -
drivers/gpu/drm/i915/i915_drv.c | 5 ++
drivers/gpu/drm/i915/i915_drv.h | 2 +
drivers/gpu/drm/i915/intel_display.c | 139 +++++++++++++++++++++++++++++---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 14 ++++
drivers/gpu/drm/i915/intel_fbdev.c | 149 +++++++----------------------------
7 files changed, 176 insertions(+), 139 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index d8eed45..805cdfe 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1318,10 +1318,6 @@ static int i915_load_modeset_init(struct drm_device *dev)
* working irqs for e.g. gmbus and dp aux transfers. */
intel_modeset_init(dev, &was_vga_enabled);
- /* Wrap existing BIOS mode configuration prior to GEM takeover */
- if (!was_vga_enabled)
- intel_fbdev_init_bios(dev);
-
ret = i915_gem_init(dev);
if (ret)
goto cleanup_power;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a78e779..a23a9c2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -154,6 +154,11 @@ module_param_named(prefault_disable, i915_prefault_disable, bool, 0600);
MODULE_PARM_DESC(prefault_disable,
"Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
+bool i915_use_bios_fb __read_mostly = 1;
+module_param_named(use_bios_fb, i915_use_bios_fb, bool, 0600);
+MODULE_PARM_DESC(use_bios_fb,
+ "Use BIOS allocated framebuffer for fbcon (default: true)");
+
static struct drm_driver driver;
extern int intel_agp_enabled;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 100d3cf..ff40c7f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -390,6 +390,7 @@ struct drm_i915_display_funcs {
* fills out the pipe-config with the hw state. */
bool (*get_pipe_config)(struct intel_crtc *,
struct intel_crtc_config *);
+ void (*get_fb_config)(struct intel_crtc *, struct intel_crtc_config *);
int (*crtc_mode_set)(struct drm_crtc *crtc,
int x, int y,
struct drm_framebuffer *old_fb);
@@ -1861,6 +1862,7 @@ extern bool i915_fastboot __read_mostly;
extern int i915_enable_pc8 __read_mostly;
extern int i915_pc8_timeout __read_mostly;
extern bool i915_prefault_disable __read_mostly;
+extern bool i915_use_bios_fb __read_mostly;
extern int i915_suspend(struct drm_device *dev, pm_message_t state);
extern int i915_resume(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f6e4792..d47f894 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1994,6 +1994,27 @@ unsigned long intel_gen4_compute_page_offset(int *x, int *y,
}
}
+int intel_format_to_fourcc(int format)
+{
+ switch (format) {
+ case DISPPLANE_8BPP:
+ return DRM_FORMAT_C8;
+ case DISPPLANE_BGRX555:
+ return DRM_FORMAT_ARGB1555;
+ case DISPPLANE_BGRX565:
+ return DRM_FORMAT_RGB565;
+ default:
+ case DISPPLANE_BGRX888:
+ return DRM_FORMAT_XRGB8888;
+ case DISPPLANE_RGBX888:
+ return DRM_FORMAT_XBGR8888;
+ case DISPPLANE_BGRX101010:
+ return DRM_FORMAT_XRGB2101010;
+ case DISPPLANE_RGBX101010:
+ return DRM_FORMAT_XBGR2101010;
+ }
+}
+
static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
int x, int y)
{
@@ -5444,6 +5465,93 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
pipe_config->port_clock = clock.dot / 5;
}
+static u32
+intel_framebuffer_pitch_for_width(int width, int bpp, bool tiled)
+{
+ u32 pitch = DIV_ROUND_UP(width * bpp, 8);
+
+ if (tiled)
+ return ALIGN(pitch, 512);
+ else
+ return ALIGN(pitch, 64);
+}
+
+static void i9xx_get_fb_config(struct intel_crtc *crtc,
+ struct intel_crtc_config *pipe_config)
+{
+ struct drm_device *dev = crtc->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_fb_config *fb_config = &pipe_config->fb_config;
+ int pipe = crtc->pipe, plane = crtc->plane, size;
+ u32 val;
+
+ WARN(1, "getting config for pipe %d\n", pipe);
+
+ val = I915_READ(DSPCNTR(plane));
+
+ if (INTEL_INFO(dev)->gen >= 4)
+ if (val & DISPPLANE_TILED)
+ fb_config->tiled = true;
+
+ fb_config->pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
+
+ switch (fb_config->pixel_format) {
+ case DISPPLANE_8BPP:
+ case DISPPLANE_YUV422:
+ fb_config->bpp = 8;
+ break;
+ case DISPPLANE_BGRX555:
+ case DISPPLANE_BGRX565:
+ case DISPPLANE_BGRA555:
+ fb_config->bpp = 16;
+ break;
+ case DISPPLANE_BGRX888:
+ case DISPPLANE_BGRA888:
+ case DISPPLANE_RGBX888:
+ case DISPPLANE_RGBA888:
+ case DISPPLANE_RGBX101010:
+ case DISPPLANE_RGBA101010:
+ case DISPPLANE_BGRX101010:
+ fb_config->bpp = 32;
+ break;
+ }
+
+ if (INTEL_INFO(dev)->gen >= 4) {
+ if (fb_config->tiled)
+ fb_config->offset = I915_READ(DSPTILEOFF(plane));
+ else
+ fb_config->offset = I915_READ(DSPLINOFF(plane));
+ fb_config->base = I915_READ(DSPSURF(plane)) & 0xfffff000;
+ } else {
+ fb_config->base = I915_READ(DSPADDR(plane));
+ }
+
+ val = I915_READ(PIPESRC(pipe));
+ fb_config->pipe_width = ((val >> 16) & 0xfff) + 1;
+ fb_config->pipe_height = ((val >> 0) & 0xfff) + 1;
+
+ val = I915_READ(HTOTAL(pipe));
+ fb_config->fb_width = (val & 0xffff) + 1;
+ val = I915_READ(VTOTAL(pipe));
+ fb_config->fb_height = (val & 0xffff) + 1;
+
+ DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x\n",
+ pipe, plane, fb_config->fb_width, fb_config->fb_height,
+ fb_config->bpp, fb_config->base);
+
+ fb_config->pitch =
+ intel_framebuffer_pitch_for_width(fb_config->fb_width,
+ fb_config->bpp,
+ fb_config->tiled);
+
+ size = ALIGN(fb_config->pitch * fb_config->fb_height, PAGE_SIZE);
+ fb_config->obj =
+ i915_gem_object_create_stolen_for_preallocated(dev,
+ fb_config->base,
+ fb_config->base,
+ size);
+}
+
static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
struct intel_crtc_config *pipe_config)
{
@@ -7621,16 +7729,10 @@ err:
}
static u32
-intel_framebuffer_pitch_for_width(int width, int bpp)
-{
- u32 pitch = DIV_ROUND_UP(width * bpp, 8);
- return ALIGN(pitch, 64);
-}
-
-static u32
intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
{
- u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
+ u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp,
+ false);
return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
}
@@ -7650,7 +7752,7 @@ intel_framebuffer_create_for_mode(struct drm_device *dev,
mode_cmd.width = mode->hdisplay;
mode_cmd.height = mode->vdisplay;
mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
- bpp);
+ bpp, false);
mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
return intel_framebuffer_create(dev, &mode_cmd, obj);
@@ -7674,7 +7776,8 @@ mode_fits_in_fbdev(struct drm_device *dev,
fb = &dev_priv->fbdev->ifb.base;
if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
- fb->bits_per_pixel))
+ fb->bits_per_pixel,
+ false))
return NULL;
if (obj->base.size < mode->vdisplay * fb->pitches[0])
@@ -10505,6 +10608,7 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.update_plane = ironlake_update_plane;
} else if (IS_VALLEYVIEW(dev)) {
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
+ dev_priv->display.get_fb_config = i9xx_get_fb_config;
dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
dev_priv->display.crtc_enable = valleyview_crtc_enable;
dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -10512,6 +10616,7 @@ static void intel_init_display(struct drm_device *dev)
dev_priv->display.update_plane = i9xx_update_plane;
} else {
dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
+ dev_priv->display.get_fb_config = i9xx_get_fb_config;
dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
dev_priv->display.crtc_enable = i9xx_crtc_enable;
dev_priv->display.crtc_disable = i9xx_crtc_disable;
@@ -10788,6 +10893,7 @@ void intel_modeset_init(struct drm_device *dev,
bool *was_vga_enabled)
{
struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *crtc;
int i, j, ret;
drm_mode_config_init(dev);
@@ -10844,6 +10950,17 @@ void intel_modeset_init(struct drm_device *dev,
/* Just in case the BIOS is doing something questionable. */
intel_disable_fbc(dev);
+
+ intel_modeset_setup_hw_state(dev, false);
+
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list,
+ base.head) {
+ if (!crtc->active)
+ continue;
+
+ if (dev_priv->display.get_fb_config)
+ dev_priv->display.get_fb_config(crtc, &crtc->config);
+ }
}
static void
@@ -11214,8 +11331,6 @@ void intel_modeset_gem_init(struct drm_device *dev)
intel_modeset_init_hw(dev);
intel_setup_overlay(dev);
-
- intel_modeset_setup_hw_state(dev, false);
}
void intel_modeset_cleanup(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 28abeea..c7137e8 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1230,7 +1230,7 @@ void ironlake_edp_panel_off(struct intel_dp *intel_dp)
WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
pp = ironlake_get_pp_control(intel_dp);
- pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
+ pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index be048d9..7b4281c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -200,6 +200,17 @@ typedef struct dpll {
int p;
} intel_clock_t;
+struct intel_fb_config {
+ int pixel_format; /* DRM fourcc code */
+ int bpp;
+ bool tiled;
+ int base, offset;
+ int fb_width, fb_height;
+ int pipe_width, pipe_height;
+ int pitch;
+ struct drm_i915_gem_object *obj;
+};
+
struct intel_crtc_config {
/**
* quirks - bitfield with hw state readout quirks
@@ -222,6 +233,8 @@ struct intel_crtc_config {
* registers. adjusted_mode.crtc_clock is the pipe pixel clock. */
struct drm_display_mode adjusted_mode;
+ struct intel_fb_config fb_config;
+
/* Pipe source size (ie. panel fitter input size)
* All planes will be positioned inside this space,
* and get clipped at the edges. */
@@ -699,6 +712,7 @@ void hsw_enable_ips(struct intel_crtc *crtc);
void hsw_disable_ips(struct intel_crtc *crtc);
void intel_display_set_init_power(struct drm_device *dev, bool enable);
int valleyview_get_vco(struct drm_i915_private *dev_priv);
+int intel_format_to_fourcc(int format);
/* intel_dp.c */
void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 2d71312..237b6e4 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -298,13 +298,6 @@ static bool pipe_enabled(struct drm_i915_private *dev_priv, enum pipe pipe)
return !!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE);
}
-static u32
-intel_framebuffer_pitch_for_width(int width, int bpp)
-{
- u32 pitch = DIV_ROUND_UP(width * bpp, 8);
- return ALIGN(pitch, 64);
-}
-
/*
* Try to read the BIOS display configuration and use it for the initial
* fb configuration.
@@ -330,119 +323,26 @@ void intel_fbdev_init_bios(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_fbdev *ifbdev;
struct drm_crtc *crtc;
+ struct intel_crtc *intel_crtc;
+ struct intel_fb_config *fb_config;
struct drm_mode_fb_cmd2 mode_cmd = { 0 };
- struct drm_i915_gem_object *obj;
- u32 obj_offset = 0;
- int mode_bpp = 0;
u32 active = 0;
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- int pipe = intel_crtc->pipe, plane = intel_crtc->plane;
- u32 val, bpp, offset, format;
- int pitch, width, height;
+ intel_crtc = to_intel_crtc(crtc);
- if (!pipe_enabled(dev_priv, pipe)) {
+ if (!pipe_enabled(dev_priv, intel_crtc->pipe)) {
DRM_DEBUG_KMS("pipe %c not active, skipping\n",
- pipe_name(pipe));
+ pipe_name(intel_crtc->pipe));
continue;
}
- val = I915_READ(DSPCNTR(plane));
-
- if (INTEL_INFO(dev)->gen >= 4) {
- if (val & DISPPLANE_TILED) {
- DRM_DEBUG_KMS("tiled BIOS fb?\n");
- continue; /* unexpected! */
- }
- }
-
- switch (val & DISPPLANE_PIXFORMAT_MASK) {
- case DISPPLANE_YUV422:
- default:
- DRM_DEBUG_KMS("pipe %c unsupported pixel format %x, skipping\n",
- pipe_name(pipe), (val & DISPPLANE_PIXFORMAT_MASK) >> 26);
- continue;
- case DISPPLANE_8BPP:
- format = DRM_FORMAT_C8;
- bpp = 8;
- break;
- case DISPPLANE_BGRX555:
- format = DRM_FORMAT_XRGB1555;
- bpp = 16;
- break;
- case DISPPLANE_BGRX565:
- format = DRM_FORMAT_RGB565;
- bpp = 16;
- break;
- case DISPPLANE_BGRX888:
- format = DRM_FORMAT_XRGB8888;
- bpp = 32;
- break;
- }
-
- if (mode_cmd.pixel_format == 0) {
- mode_bpp = bpp;
- mode_cmd.pixel_format = format;
- }
-
- if (mode_cmd.pixel_format != format) {
- DRM_DEBUG_KMS("pipe %c has format/bpp (%d, %d) mismatch: skipping\n",
- pipe_name(pipe), format, bpp);
- continue;
- }
-
- if (INTEL_INFO(dev)->gen >= 4) {
- if (I915_READ(DSPTILEOFF(plane))) {
- DRM_DEBUG_KMS("pipe %c is offset: skipping\n",
- pipe_name(pipe));
- continue;
- }
-
- offset = I915_READ(DSPSURF(plane)) & 0xfffff000;
- } else {
- offset = I915_READ(DSPADDR(plane));
- }
- if (!obj_offset)
- obj_offset = offset;
-
- if (offset != obj_offset) {
- DRM_DEBUG_KMS("multiple pipe setup not in clone mode, skipping\n");
- continue;
- }
-
- val = I915_READ(PIPESRC(pipe));
- width = ((val >> 16) & 0xfff) + 1;
- height = ((val >> 0) & 0xfff) + 1;
-
- /* Adjust fitted modes */
- val = I915_READ(HTOTAL(pipe));
- if (((val & 0xffff) + 1) != width) {
- DRM_DEBUG_DRIVER("BIOS fb not native width (%d vs %d), overriding\n", width, (val & 0xffff) + 1);
- width = (val & 0xffff) + 1;
- }
- val = I915_READ(VTOTAL(pipe));
- if (((val & 0xffff) + 1) != height) {
- DRM_DEBUG_DRIVER("BIOS fb not native height (%d vs %d), overriding\n", height, (val & 0xffff) + 1);
- height = (val & 0xffff) + 1;
- }
-
- DRM_DEBUG_KMS("Found active pipe [%d/%d]: size=%dx%d@%d, offset=%x\n",
- pipe, plane, width, height, bpp, offset);
-
- if (width > mode_cmd.width)
- mode_cmd.width = width;
-
- if (height > mode_cmd.height)
- mode_cmd.height = height;
-
- pitch = intel_framebuffer_pitch_for_width(width, bpp);
- if (pitch > mode_cmd.pitches[0])
- mode_cmd.pitches[0] = pitch;
-
- active |= 1 << pipe;
+ active |= 1 << intel_crtc->pipe;
+ break;
}
+ fb_config = &intel_crtc->config.fb_config;
+
if (active == 0) {
DRM_DEBUG_KMS("no active pipes found, not using BIOS config\n");
return;
@@ -455,23 +355,19 @@ void intel_fbdev_init_bios(struct drm_device *dev)
}
ifbdev->stolen = true;
- ifbdev->preferred_bpp = mode_bpp;
+ ifbdev->preferred_bpp = fb_config->bpp;
ifbdev->helper.funcs = &intel_fb_helper_funcs;
ifbdev->helper.funcs->initial_config = intel_fb_initial_config;
- /* assume a 1:1 linear mapping between stolen and GTT */
- obj = i915_gem_object_create_stolen_for_preallocated(dev,
- obj_offset,
- obj_offset,
- ALIGN(mode_cmd.pitches[0] * mode_cmd.height, PAGE_SIZE));
- if (obj == NULL) {
- DRM_DEBUG_KMS("failed to create stolen fb\n");
- goto out_free_ifbdev;
- }
+ mode_cmd.pixel_format = intel_format_to_fourcc(fb_config->pixel_format);
+ mode_cmd.width = fb_config->fb_width;
+ mode_cmd.height = fb_config->fb_height;
+ mode_cmd.pitches[0] = fb_config->pitch;
mutex_lock(&dev->struct_mutex);
- if (intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, obj)) {
+ if (intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd,
+ fb_config->obj)) {
DRM_DEBUG_KMS("intel fb init failed\n");
goto out_unref_obj;
}
@@ -481,6 +377,13 @@ void intel_fbdev_init_bios(struct drm_device *dev)
if ((active & (1 << to_intel_crtc(crtc)->pipe)) == 0)
continue;
+ /*
+ * This should only fail on the first one so we don't need
+ * to cleanup any secondary crtc->fbs
+ */
+ if (intel_pin_and_fence_fb_obj(dev, fb_config->obj, NULL))
+ goto out_unref_obj;
+
crtc->fb = &ifbdev->ifb.base;
}
@@ -492,8 +395,7 @@ void intel_fbdev_init_bios(struct drm_device *dev)
out_unref_obj:
mutex_unlock(&dev->struct_mutex);
- drm_gem_object_unreference_unlocked(&obj->base);
-out_free_ifbdev:
+ drm_gem_object_unreference_unlocked(&fb_config->obj->base);
kfree(ifbdev);
}
@@ -503,6 +405,9 @@ int intel_fbdev_init(struct drm_device *dev)
struct drm_i915_private *dev_priv = dev->dev_private;
int ret;
+ if (i915_use_bios_fb)
+ intel_fbdev_init_bios(dev);
+
if ((ifbdev = dev_priv->fbdev) == NULL) {
ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL);
if (ifbdev == NULL)
--
1.8.4.2
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