[Intel-gfx] [PATCH] Workaround for flicker with panning on the i830

[Daniel Vetter]

On Tue, Nov 12, 2013 at 05:41:12PM +0100, Thomas Richter wrote:
> Am 11.11.2013 16:43, schrieb Daniel Vetter:
> >Oh, that's really interesting. gen2 has a unified display fifo on
> >machines that support 2 outputs. DSPARB tells the hw how to exactly
> >split this up between the two pipes. There are two bit ranges of
> >interest here:
> 
> /* snip */
> 
> Hmm, why I understand *that* it does make a difference, I do not
> understand the details.
> By a unified display fifo do you mean that the display output has an
> internal buffer memory (the fifo) which
> basically feeds the the DVOs or the LVDS with memory, which comes
> via DMA into the fifo. Is that right?

Yup. The fifo is there ot paper over memory fetch latencies. The memory
controller sends 64b blocks, but the display output needs to be continous.

> By "split", do you mean that a fixed amount of bytes (or rather,
> lines as in multiples of 16 bytes) are allocated for each
> participating pipe?

Yup.

> Simply enlarging the fifo does not help (i.e. writing a larger value
> into the register). Just the positions where I get the flicker
> change, but the problem does not go away. So whatever needs to be
> done is to adjust this register according to the alignment of the
> base address of the corresponding DMA engine that feeds the pipe.

Hm, that's strange.

> >What we'd need to do here is to update this register when switching
> >the number of active display pipes in the ->modeset_global_resources
> >hook. We also need to make sure we have updated watermark values set
> >up already, before rewriting the value of DSPARB (since the watermarks
> >depend upon the size of the fifo).
> >
> >For I start I'd go with splitting the fifo according to the display
> >clock between plane A and B and giving nothing to plane C. We don't
> >have any code to use plane C so giving everything to just A and B is
> >better.
> 
> By that you mean "BEND = maximum" and "AEND" in between? That does
> not seem to be sufficient. It needs to be modified according to the
> buffer alignment, and sometimes smaller values work, sometimes
> larger ones.

Yeah, I've meant BEND = max and AEND split so that the two resulting sizes
are proportional to the pixel clock (i.e. both pipes should take equal
amount of time roughly to go through the full fifo). Indeed really strang
that this doesn't seem to work.

Looking at docs I don't see any mention of a w/a :(

The only (totally crazy) idea I have is that the fifo falls over if it
fetches accross a tile/page boundary. But no idea how to figure out a
formula that'd work everywhere ...

To simplify things I'd start with just just one pipe display to VGA and
then going through different resolutions and different offset. Maybe
there's a pattern in the display fifo lenghts that work.

Happy hacking!

Cheers, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch