[Intel-gfx] [PATCH] drm/i915: Update rps interrupt limits

[jeff.mcgee at intel.com]

From: Jeff McGee <jeff.mcgee at intel.com>

This bug was found on OTC Haswell Android product which makes use of
sysfs to set rps min and max range at boot.

This patch follows the original patch in implementing the fix with
a minimum of code change, which was desirable for late
stage product. A cleaner fix might involve refactoring the rps
interface a bit by perhaps making gen6_rps_limits a public function
that could be called from debugfs with the desired min/max. And the
register update could be placed in that function. Let me know if
something like that is more desirable for upstream and provide any
thoughts on form.

I also noticed that writing the interrupt limits register has been
removed for Valleyview recently by Chris Wilson, so I have removed
those parts of the original patch. I guess that means that it is
not relevant for Valleyview?

Jeff McGee (1):
  drm/i915: Update rps interrupt limits

 drivers/gpu/drm/i915/i915_sysfs.c | 10 ++++++++++
 drivers/gpu/drm/i915/intel_pm.c   | 10 +++++++++-
 2 files changed, 19 insertions(+), 1 deletion(-)

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1.8.4.2