[Intel-gfx] [PATCH 1/2] drm/i915: Report all GTFIFODBG errors

[Ville Syrjälä]

On Thu, Nov 14, 2013 at 07:09:48PM +0200, Ville Syrjälä wrote:
> On Thu, Nov 14, 2013 at 02:54:10PM +0200, Mika Kuoppala wrote:
> > ville.syrjala at linux.intel.com writes:
> > 
> > > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > >
> > > On VLV GTFIFODBG has more bits. Just report them all.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/i915_reg.h     | 5 ++++-
> > >  drivers/gpu/drm/i915/intel_uncore.c | 5 ++---
> > >  2 files changed, 6 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 849e595..e8f47de 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -4852,7 +4852,10 @@
> > >  #define    FORCEWAKE_MT_ENABLE			(1<<5)
> > >  
> > >  #define  GTFIFODBG				0x120000
> > > -#define    GT_FIFO_CPU_ERROR_MASK		7
> > > +#define    GT_FIFO_SBDROPERR			(1<<6)
> > > +#define    GT_FIFO_BLOBDROPERR			(1<<5)
> > > +#define    GT_FIFO_SB_READ_ABORTERR		(1<<4)
> > > +#define    GT_FIFO_DROPERR			(1<<3)
> > >  #define    GT_FIFO_OVFERR			(1<<2)
> > >  #define    GT_FIFO_IAWRERR			(1<<1)
> > >  #define    GT_FIFO_IARDERR			(1<<0)
> > > diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> > > index 0edabbb..a9849ab 100644
> > > --- a/drivers/gpu/drm/i915/intel_uncore.c
> > > +++ b/drivers/gpu/drm/i915/intel_uncore.c
> > > @@ -121,9 +121,8 @@ static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
> > >  	u32 gtfifodbg;
> > >  
> > >  	gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
> > > -	if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
> > > -	     "MMIO read or write has been dropped %x\n", gtfifodbg))
> > > -		__raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
> > > +	if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
> > 
> > I think you still need mask, there are ro fields != 0 in the same
> > register.
> 
> Which bits? VLV has those seven low bits, others just three low bits
> AFAICS.

OK, so the problem is that bspec seems to list some bogus junk for these
registers. The gunit register HAS is what I used to write these patches.
Someone with a VLV on their hands should double check whether real
hardware agrees with the gunit register HAS. Any volunteers?

-- 
Ville Syrjälä
Intel OTC