[Intel-gfx] [PATCH 04/10] drm/i915: Limit FBC flush to post batch flush

[Rodrigo Vivi]

On Wed, Nov 06, 2013 at 11:02:19PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Don't issue the FBC nuke/cache clean command when invalidate_domains!=0.

Double negative almost confused me, but all right here.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>

> That would indicate that we're not being called for the post-batch
> flush.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index e32c08a..752f208 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -354,7 +354,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring,
>  	intel_ring_emit(ring, 0);
>  	intel_ring_advance(ring);
>  
> -	if (flush_domains)
> +	if (!invalidate_domains && flush_domains)
>  		return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
>  
>  	return 0;
> @@ -1837,7 +1837,7 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
>  	}
>  	intel_ring_advance(ring);
>  
> -	if (IS_GEN7(dev) && flush)
> +	if (IS_GEN7(dev) && !invalidate && flush)
>  		return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
>  
>  	return 0;
> -- 
> 1.8.1.5
> 
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