[Intel-gfx] [PATCH 05/10] drm/i915: Emit SRM after the MSG_FBC_REND_STATE LRI
Rodrigo Vivi
rodrigo.vivi at gmail.com
Wed Nov 20 23:50:15 CET 2013
Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
On Wed, Nov 06, 2013 at 11:02:20PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> The spec tells us that we need to emit an SRM after the LRI
> to MSG_FBC_REND_STATE.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 6 ++++--
> 2 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0719c8b..7a4d3e1 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -235,6 +235,7 @@
> */
> #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
> #define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1)
> +#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
> #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
> #define MI_FLUSH_DW_STORE_INDEX (1<<21)
> #define MI_INVALIDATE_TLB (1<<18)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 752f208..4649bf5 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -285,14 +285,16 @@ static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
> if (!ring->fbc_dirty)
> return 0;
>
> - ret = intel_ring_begin(ring, 4);
> + ret = intel_ring_begin(ring, 6);
> if (ret)
> return ret;
> - intel_ring_emit(ring, MI_NOOP);
> /* WaFbcNukeOn3DBlt:ivb/hsw */
> intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
> intel_ring_emit(ring, MSG_FBC_REND_STATE);
> intel_ring_emit(ring, value);
> + intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
> + intel_ring_emit(ring, MSG_FBC_REND_STATE);
> + intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
> intel_ring_advance(ring);
>
> ring->fbc_dirty = false;
> --
> 1.8.1.5
>
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