[Intel-gfx] [PATCH 9/9] drm/i915: Enable pipe gamma for sprites

Daniel Vetter daniel at ffwll.ch
Thu Nov 21 09:10:58 CET 2013


On Tue, Nov 19, 2013 at 09:42:55AM -0800, Rodrigo Vivi wrote:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
> 
> On Mon, Nov 18, 2013 at 6:32 PM, Rodrigo Vivi <rodrigo.vivi at gmail.com> wrote:
> > From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> >
> > We send the primary and cursor plane data through the gamma unit.
> > In order to get matching output from sprites, also send the sprite
> > data through the gamma unit.
> >
> > In the future we should add some properties to control this
> > explicitly, and also add properties for the per-sprite gamma ramps
> > what have you, but for now this seems like a reasonable thing to do.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>

Eventually we want testcases for this, but I think that's only really
useful once we expose a "bypasss gamma" or similar property. And that is
best done together with exposing all the other csc stuff I'd say. So
merged.
-Daniel

> > ---
> >  drivers/gpu/drm/i915/i915_reg.h     |  2 +-
> >  drivers/gpu/drm/i915/intel_sprite.c | 18 ++++++++++++++++++
> >  2 files changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 8f4916d..7b454d2 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3745,7 +3745,7 @@
> >
> >  #define _SPACNTR               (VLV_DISPLAY_BASE + 0x72180)
> >  #define   SP_ENABLE                    (1<<31)
> > -#define   SP_GEAMMA_ENABLE             (1<<30)
> > +#define   SP_GAMMA_ENABLE              (1<<30)
> >  #define   SP_PIXFORMAT_MASK            (0xf<<26)
> >  #define   SP_FORMAT_YUV422             (0<<26)
> >  #define   SP_FORMAT_BGR565             (5<<26)
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> > index 8afaad6..cb7ffd3 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -104,6 +104,12 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
> >                 break;
> >         }
> >
> > +       /*
> > +        * Enable gamma to match primary/cursor plane behaviour.
> > +        * FIXME should be user controllable via propertiesa.
> > +        */
> > +       sprctl |= SP_GAMMA_ENABLE;
> > +
> >         if (obj->tiling_mode != I915_TILING_NONE)
> >                 sprctl |= SP_TILED;
> >
> > @@ -257,6 +263,12 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> >                 BUG();
> >         }
> >
> > +       /*
> > +        * Enable gamma to match primary/cursor plane behaviour.
> > +        * FIXME should be user controllable via propertiesa.
> > +        */
> > +       sprctl |= SPRITE_GAMMA_ENABLE;
> > +
> >         if (obj->tiling_mode != I915_TILING_NONE)
> >                 sprctl |= SPRITE_TILED;
> >
> > @@ -453,6 +465,12 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
> >                 BUG();
> >         }
> >
> > +       /*
> > +        * Enable gamma to match primary/cursor plane behaviour.
> > +        * FIXME should be user controllable via propertiesa.
> > +        */
> > +       dvscntr |= DVS_GAMMA_ENABLE;
> > +
> >         if (obj->tiling_mode != I915_TILING_NONE)
> >                 dvscntr |= DVS_TILED;
> >
> > --
> > 1.8.3.1
> >
> 
> 
> 
> -- 
> Rodrigo Vivi
> Blog: http://blog.vivi.eng.br
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch



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