[Intel-gfx] [PATCH] drm/i915: Prefer setting PTE cache age to 3

[Eric Anholt]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> We have conflicting benchmark data that suggest either age 0 or age 3 is
> better. However, the earlier benchmark on which we based the switch to
> age 0
>
> (commit 0d8ff15e9a15f2b393e53337a107b7a1e5919b6d
> Author: Ben Widawsky <benjamin.widawsky at intel.com>
> Date:   Thu Jul 4 11:02:03 2013 -0700
>
>     drm/i915/hsw: Set correct Haswell PTE encodings)
>
> actually seems to prefer the default PTE encoding as age 3. Presumably,
> this is in part due to the use of MOCS to override the PTE encodings
> when appropriate.

This bothered me when reviewing the kernel code for hsw.  Thanks.

Reviewed-by: Eric Anholt <eric at anholt.net>

Note that userspace doesn't currently set MOCS other than the L3 bit.
I'm hoping we end up not having to, since we don't have a WT option in
MOCS other than "just listen to the PTEs".
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