[Intel-gfx] [PATCH 3/4] tests/gem_exec_parse: Add tests for register whitelist

[bradley.d.volkin at intel.com]

From: Brad Volkin <bradley.d.volkin at intel.com>

Signed-off-by: Brad Volkin <bradley.d.volkin at intel.com>
---
 tests/gem_exec_parse.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c
index b34fe1b..d4136db 100644
--- a/tests/gem_exec_parse.c
+++ b/tests/gem_exec_parse.c
@@ -141,6 +141,7 @@ int fd;
 
 #define MI_ARB_ON_OFF (0x8 << 23)
 #define MI_DISPLAY_FLIP ((0x14 << 23) | 1)
+#define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1)
 
 #define GFX_OP_PIPE_CONTROL	((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
 #define   PIPE_CONTROL_QW_WRITE	(1<<14)
@@ -213,6 +214,31 @@ igt_main
 				      -EINVAL));
 	}
 
+	igt_subtest("registers") {
+		uint32_t lri_bad[] = {
+			MI_LOAD_REGISTER_IMM,
+			0, // disallowed register address
+			0x12000000,
+			MI_BATCH_BUFFER_END,
+		};
+		uint32_t lri_ok[] = {
+			MI_LOAD_REGISTER_IMM,
+			0x5280, // allowed register address (SO_WRITE_OFFSET[0])
+			0x1,
+			MI_BATCH_BUFFER_END,
+		};
+		igt_assert(
+			   exec_batch(fd, handle,
+				      lri_bad, sizeof(lri_bad),
+				      I915_EXEC_RENDER,
+				      -EINVAL));
+		igt_assert(
+			   exec_batch(fd, handle,
+				      lri_ok, sizeof(lri_ok),
+				      I915_EXEC_RENDER,
+				      0));
+	}
+
 	igt_fixture {
 		gem_close(fd, handle);
 
-- 
1.8.4.4