[Intel-gfx] [PATCH 1/2] drm/i915/vlv: use a lower RC6 timeout on VLV

[S, Deepak]

Patches looks fine.

Reviewed-by: Deepak S <deepak.s at inel.com<mailto:jbarnes at virtuousgeek.org>>



From: Jesse Barnes <jbarnes at virtuousgeek.org<mailto:jbarnes at virtuousgeek.org>>
Date: Fri, Nov 15, 2013 at 11:02 PM
Subject: [Intel-gfx] [PATCH 1/2] drm/i915/vlv: use a lower RC6 timeout on VLV
To: intel-gfx at lists.freedesktop.org<mailto:intel-gfx at lists.freedesktop.org>


We use timeout mode, and we need to lower the timeout to get good RC6
residency when loads are running.  This gets me from 0% residency during
glxgears to 77%, which is a pretty good improvement.  This value also
matches the current BWG recommentations.

Tested-by: "Meng, Mengmeng" <mengmeng.meng at intel.com<mailto:mengmeng.meng at intel.com>>
Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org<mailto:jbarnes at virtuousgeek.org>>
---
 drivers/gpu/drm/i915/intel_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 172efa0..5d3912a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4102,7 +4102,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
        for_each_ring(ring, dev_priv, i)
                I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);

-       I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
+       I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);

        /* allows RC6 residency counter to work */
        I915_WRITE(VLV_COUNTER_CONTROL,
--
1.8.4.2

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--
Deepak S
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