[Intel-gfx] [PATCH 5/8] intel-gtt: Use i810_write_entry() on gen2 platforms

[ville.syrjala at linux.intel.com]

From: Ville Syrjälä <ville.syrjala at linux.intel.com>

i810_write_entry() is identical to i830_write_entry(), except the the
use of the AGP_DCACHE_MEMORY flag to signal that the PTE should be
encoded with I810_PTE_LOCAL. We want that on i830 if we have local
memory. So simply swap all gen2 machines over to i810_write_entry()

Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
---
 drivers/char/agp/intel-gtt.c | 15 ++-------------
 1 file changed, 2 insertions(+), 13 deletions(-)

diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 35788a2..35a667d 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -743,17 +743,6 @@ static void i830_chipset_flush(void)
 	}
 }
 
-static void i830_write_entry(dma_addr_t addr, unsigned int entry,
-			     unsigned int flags)
-{
-	u32 pte_flags = I810_PTE_VALID;
-
-	if (flags ==  AGP_USER_CACHED_MEMORY)
-		pte_flags |= I830_PTE_SYSTEM_CACHED;
-
-	writel(addr | pte_flags, intel_private.gtt + entry);
-}
-
 bool intel_enable_gtt(void)
 {
 	u8 __iomem *reg;
@@ -1196,7 +1185,7 @@ static const struct intel_gtt_driver i8xx_gtt_driver = {
 	.has_pgtbl_enable = 1,
 	.setup = i830_setup,
 	.cleanup = i830_cleanup,
-	.write_entry = i830_write_entry,
+	.write_entry = i810_write_entry,
 	.dma_mask_size = 32,
 	.check_flags = i830_check_flags,
 	.chipset_flush = i830_chipset_flush,
@@ -1207,7 +1196,7 @@ static const struct intel_gtt_driver i915_gtt_driver = {
 	.setup = i9xx_setup,
 	.cleanup = i9xx_cleanup,
 	/* i945 is the last gpu to need phys mem (for overlay and cursors). */
-	.write_entry = i830_write_entry,
+	.write_entry = i810_write_entry,
 	.dma_mask_size = 32,
 	.check_flags = i830_check_flags,
 	.chipset_flush = i9xx_chipset_flush,
-- 
1.8.3.2