[Intel-gfx] [PATCH 4/4] drm/i915: implement the Haswell mode set sequence workaround

Daniel Vetter daniel at ffwll.ch
Tue Oct 1 21:24:49 CEST 2013

On Fri, Sep 20, 2013 at 04:21:19PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
> This workaround is described in the mode set sequence documentation.
> When enabling planes for the second pipe, we need to wait for 2
> vblanks on the first pipe. This should solve "a flash of screen
> corruption if planes are enabled on second/third pipe during the time
> that big FIFO mode is exiting". Watermarks are fun :)
> v2: Save indentation levels
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>

Last two patches of this series merged to dinq.

Thanks, Daniel
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

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