[Intel-gfx] [PATCH] drm/i915/hsw: Disable L3 caching of atomic memory operations.

[Daniel Vetter]

On Wed, Oct 02, 2013 at 03:53:16PM -0700, Francisco Jerez wrote:
> Otherwise using any atomic memory operation will lock up the GPU due
> to a Haswell hardware bug.
> 
> v2: Use the _MASKED_BIT_ENABLE macro.  Drop drm parameter definition.
> 
> Signed-off-by: Francisco Jerez <currojerez at riseup.net>
> Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
> Cc: Daniel Vetter <daniel at ffwll.ch>
> Cc: <stable at vger.kernel.org>

Picked up for -fixes, thanks for the patch. Checkpatch was a bit unhappy
about the whitespace, so I've rectified that while applying.
-Daniel
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
>  drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c159e1a..38f96f6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3881,6 +3881,9 @@
>  #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG		0x9030
>  #define  GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB	(1<<11)
>  
> +#define HSW_SCRATCH1				0xb038
> +#define  HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE	(1<<27)
> +
>  #define HSW_FUSE_STRAP		0x42014
>  #define  HSW_CDCLK_LIMIT	(1 << 24)
>  
> @@ -4728,6 +4731,9 @@
>  #define GEN7_ROW_CHICKEN2_GT2		0xf4f4
>  #define   DOP_CLOCK_GATING_DISABLE	(1<<0)
>  
> +#define HSW_ROW_CHICKEN3		0xe49c
> +#define  HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE    (1 << 6)
> +
>  #define G4X_AUD_VID_DID			(dev_priv->info->display_mmio_offset + 0x62020)
>  #define INTEL_AUDIO_DEVCL		0x808629FB
>  #define INTEL_AUDIO_DEVBLC		0x80862801
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index dd176b7..556abc6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4955,6 +4955,11 @@ static void haswell_init_clock_gating(struct drm_device *dev)
>  	I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
>  			GEN7_WA_L3_CHICKEN_MODE);
>  
> +	/* L3 caching of data atomics doesn't work -- disable it. */
> +	I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
> +	I915_WRITE(HSW_ROW_CHICKEN3,
> +                _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
> +
>  	/* This is required by WaCatErrorRejectionIssue:hsw */
>  	I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
>  			I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
> -- 
> 1.8.3.4
> 

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch