[Intel-gfx] [PATCH 2/2] drm/i915/dp: update training set in a burst write with training pattern set

[Ville Syrjälä]

On Fri, Oct 04, 2013 at 03:08:48PM +0300, Jani Nikula wrote:
> The DP spec allows this, and requires it when full link training is
> started with non-minimum voltage swing and/or non-zero pre-emphasis.
> 
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>

Looks good.

For the series:
Reviewed-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

> ---
>  drivers/gpu/drm/i915/intel_dp.c |   28 ++++++++++++++--------------
>  1 file changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 0ed7717..bfd0e76 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2314,7 +2314,8 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
>  	enum port port = intel_dig_port->port;
> -	int ret;
> +	uint8_t buf[sizeof(intel_dp->train_set) + 1];
> +	int ret, len;
>  
>  	if (HAS_DDI(dev)) {
>  		uint32_t temp = I915_READ(DP_TP_CTL(port));
> @@ -2384,22 +2385,21 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
>  	I915_WRITE(intel_dp->output_reg, *DP);
>  	POSTING_READ(intel_dp->output_reg);
>  
> -	ret = intel_dp_aux_native_write_1(intel_dp, DP_TRAINING_PATTERN_SET,
> -					  dp_train_pat);
> -	if (ret != 1)
> -		return false;
> -
> -	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
> +	buf[0] = dp_train_pat;
> +	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
>  	    DP_TRAINING_PATTERN_DISABLE) {
> -		ret = intel_dp_aux_native_write(intel_dp,
> -						DP_TRAINING_LANE0_SET,
> -						intel_dp->train_set,
> -						intel_dp->lane_count);
> -		if (ret != intel_dp->lane_count)
> -			return false;
> +		/* don't write DP_TRAINING_LANEx_SET on disable */
> +		len = 1;
> +	} else {
> +		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
> +		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
> +		len = intel_dp->lane_count + 1;
>  	}
>  
> -	return true;
> +	ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
> +					buf, len);
> +
> +	return ret == len;
>  }
>  
>  static bool
> -- 
> 1.7.9.5

-- 
Ville Syrjälä
Intel OTC