[Intel-gfx] [PATCH 2/2] [v2] drm/i915: Disable GGTT PTEs on GEN6+ suspend

Chris Wilson chris at chris-wilson.co.uk
Wed Oct 16 19:27:33 CEST 2013

On Wed, Oct 16, 2013 at 10:06:27AM -0700, Ben Widawsky wrote:
> On Wed, Oct 16, 2013 at 05:58:31PM +0100, Chris Wilson wrote:
> > So clearing the valid bit should result in the GPU reporting errors for
> > delayed accesses, but none were reported?
> So I can't actually reproduce the problem for some reason. Paulo will
> need to answer. One theory is the fault information is lost on suspend.
> The original patch put faults both in suspend, and resume. After this, I
> asked Paulo to wedge the GPU, and there I saw faults.

If we can capture the error, and it should be very possible to do so, we
should be able to pinpoint the cause quite quickly. If it is just deferred
writes, it should also be a problem across module unload - which should
be easier for getting debug information out.

Chris Wilson, Intel Open Source Technology Centre

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