[Intel-gfx] [PATCH 0/4] drm/i915: Baytrail MIPI DSI support Updated
shobhit.kumar at intel.com
Mon Oct 21 14:21:03 CEST 2013
Hi All -
These patches enhance the current support for MIPI DSI for Baytrail. They
continue on the sub-encoder design and adds few more dev_ops to handle
sequence correctly. Major changes are -
1. DSI Clock calculation based on pixel clock
2. Add new dev_ops for better sequencing the enable/disable path
3. Parameterized the hardcoded DSI parameters. These also forms building
block for the generic MIPI driver to come in future based on enhancements
in VBT. All these parameters are initialized or computed in the sub-encoder
driver. Some of them might look unneccesary for now.
I am also aware of the drm_bridge support now comming in and will in future
migrate from sub-encoder design to drm_bridge.
This DSI sequence has been validated with couple of test panels and is working now.
Still no sub-encoder driver is included and this support will be mostly be disabled
untill a panel sub-encoder driver is added. Proper detection or VBT is still pending.
Shobhit Kumar (4):
drm/i915: Add more dev ops for MIPI sub encoder
drm/i915: Use FLISDSI interface for band gap reset
drm/i915: Compute dsi_clk from pixel clock
drm/i915: Parameterize the MIPI enabling sequnece and adjust the
drivers/gpu/drm/i915/i915_drv.h | 13 ++
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dsi.c | 378 +++++++++++++++++----------------
drivers/gpu/drm/i915/intel_dsi.h | 29 +++
drivers/gpu/drm/i915/intel_dsi_pll.c | 75 +++++--
drivers/gpu/drm/i915/intel_sideband.c | 14 ++
6 files changed, 318 insertions(+), 192 deletions(-)
More information about the Intel-gfx