[Intel-gfx] [PATCH] drm/i915: Sanitize the PPT fdi lane bifurcate state on ivb

[Daniel Vetter]

We expect this bit to be always set when possible, but some BIOSes are
lazy and don't do this. The result is a pile of WARNs and unhappy fdi
link training code ...

v2: It's actually the inverse: The BIOS sets this bit when it's not
strictly needed. This should be cleaned up in the
global_modeset_resources callback, but we've failed to look at the
active bit. Which means this won't fire (and so clean up BIOS state)
when enabling pipe B or C for the first time.

v3: Wrap lines.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70507
Tested-by: Jan-Michael Brummer <jan.brummer at tabos.org>
Cc: stable at vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index cfe9e709..3569db6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2421,9 +2421,10 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
 			   FDI_FE_ERRC_ENABLE);
 }
 
-static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
+static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
 {
-	return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
+	return crtc->base.enabled && crtc->active &&
+		crtc->config.has_pch_encoder;
 }
 
 static void ivb_modeset_global_resources(struct drm_device *dev)
-- 
1.8.4.rc3