[Intel-gfx] [PATCH] [trivial] drm/i915: Convert straggling MCHBAR registers

[Jani Nikula]

On Wed, 23 Oct 2013, Ben Widawsky <benjamin.widawsky at intel.com> wrote:
> All our registers which are written through the MCHBAR are defined
> descriptively as an offset to the MCHBAR. We had 3 outliers here.
> Convert these as well so all registers which are offsets are MCHBAR can
> be easily identified/found within the code.
>
> With this, convert DCLK to also follow this format.
>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>

Reviewed-by: Jani Nikula <jani.nikula at intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
>  drivers/gpu/drm/i915/intel_pm.c | 2 +-
>  2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2b4f7b1..6c98238 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1480,7 +1480,7 @@
>  #define MCHBAR_MIRROR_BASE_SNB	0x140000
>  
>  /* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
> -#define DCLK 0x5e04
> +#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
>  
>  /** 915-945 and GM965 MCH register controlling DRAM channel access */
>  #define DCC			0x10200
> @@ -1775,9 +1775,9 @@
>  #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
>  #define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
>  
> -#define GEN6_GT_PERF_STATUS	0x145948
> -#define GEN6_RP_STATE_LIMITS	0x145994
> -#define GEN6_RP_STATE_CAP	0x145998
> +#define GEN6_GT_PERF_STATUS	(MCHBAR_MIRROR_BASE_SNB + 0x5948)
> +#define GEN6_RP_STATE_LIMITS	(MCHBAR_MIRROR_BASE_SNB + 0x5994)
> +#define GEN6_RP_STATE_CAP	(MCHBAR_MIRROR_BASE_SNB + 0x5998)
>  
>  /*
>   * Logical Context regs
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3e140ab..d4dd543 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3915,7 +3915,7 @@ void gen6_update_ring_freq(struct drm_device *dev)
>  	/* Convert from kHz to MHz */
>  	max_ia_freq /= 1000;
>  
> -	min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
> +	min_ring_freq = I915_READ(DCLK) & 0xf;
>  	/* convert DDR frequency from units of 266.6MHz to bandwidth */
>  	min_ring_freq = mult_frac(min_ring_freq, 8, 3);
>  
> -- 
> 1.8.4.1
>
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-- 
Jani Nikula, Intel Open Source Technology Center